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offset bank coordinates

This commit is contained in:
Jesse Cirimelli-Low 2021-05-03 15:51:53 -07:00
parent 4377619bf6
commit 14e087a5eb
2 changed files with 2 additions and 1 deletions
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2
compiler/modules/bank.py
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@ -72,7 +72,7 @@ class bank(design.design):
# self.add_lvs_correspondence_points() # self.add_lvs_correspondence_points()
# Remember the bank center for further placement # Remember the bank center for further placement
#self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1)
self.bank_array_ur = self.bitcell_array_inst.ur() self.bank_array_ur = self.bitcell_array_inst.ur()
self.bank_array_ul = self.bitcell_array_inst.ul() self.bank_array_ul = self.bitcell_array_inst.ul()
self.DRC_LVS() self.DRC_LVS()

1
compiler/sram/sram_1bank.py
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@ -140,6 +140,7 @@ class sram_1bank(sram_base):
# This includes 2 M2 pitches for the row addr clock line. # This includes 2 M2 pitches for the row addr clock line.
# The delay line is aligned with the bitcell array while the control logic is aligned with the port_data # The delay line is aligned with the bitcell array while the control logic is aligned with the port_data
# using the control_logic_center value. # using the control_logic_center value.
breakpoint()
self.control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch, self.control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch,
self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y) self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
self.control_logic_insts[port].place(self.control_pos[port]) self.control_logic_insts[port].place(self.control_pos[port])