mirror of https://github.com/VLSIDA/OpenRAM.git
Why was single port decoder test a dual port?
This commit is contained in:
parent
493c9125f1
commit
147649e142
|
|
@ -23,7 +23,7 @@ class hierarchical_decoder_test(openram_test):
|
||||||
globals.init_openram(config_file)
|
globals.init_openram(config_file)
|
||||||
|
|
||||||
OPTS.num_rw_ports = 1
|
OPTS.num_rw_ports = 1
|
||||||
OPTS.num_r_ports = 1
|
OPTS.num_r_ports = 0
|
||||||
OPTS.num_w_ports = 0
|
OPTS.num_w_ports = 0
|
||||||
globals.setup_bitcell()
|
globals.setup_bitcell()
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue