mirror of https://github.com/VLSIDA/OpenRAM.git
Change hierchical decoder output order to match changes to netlist.
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b5b691b73d
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@ -523,8 +523,8 @@ class hierarchical_decoder(design.design):
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"""
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"""
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row_index = 0
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row_index = 0
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if (self.num_inputs == 4 or self.num_inputs == 5):
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if (self.num_inputs == 4 or self.num_inputs == 5):
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for index_A in self.predec_groups[0]:
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for index_B in self.predec_groups[1]:
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for index_B in self.predec_groups[1]:
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for index_A in self.predec_groups[0]:
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# FIXME: convert to connect_bus?
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# FIXME: convert to connect_bus?
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predecode_name = "predecode_{}".format(index_A)
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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@ -533,9 +533,9 @@ class hierarchical_decoder(design.design):
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row_index = row_index + 1
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row_index = row_index + 1
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elif (self.num_inputs > 5):
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elif (self.num_inputs > 5):
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for index_A in self.predec_groups[0]:
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for index_C in self.predec_groups[2]:
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for index_B in self.predec_groups[1]:
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for index_B in self.predec_groups[1]:
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for index_C in self.predec_groups[2]:
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for index_A in self.predec_groups[0]:
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# FIXME: convert to connect_bus?
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# FIXME: convert to connect_bus?
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predecode_name = "predecode_{}".format(index_A)
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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