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fix missed self.left_rbl refactor

This commit is contained in:
jcirimel 2020-10-06 05:11:15 -07:00
parent 888646cdf9
commit 13e2a9f5f7
1 changed files with 2 additions and 2 deletions
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4
compiler/modules/replica_bitcell_array.py
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@ -166,7 +166,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
cols=1, cols=1,
column_offset=0, column_offset=0,
rows=self.row_size + self.extra_rows, rows=self.row_size + self.extra_rows,
mirror=(self.left_rbl + 1) % 2) mirror=(self.rbl[0] + 1) % 2)
self.add_mod(self.row_cap_left) self.add_mod(self.row_cap_left)
self.row_cap_right = factory.create(module_type=row_cap_module_type, self.row_cap_right = factory.create(module_type=row_cap_module_type,
@ -177,7 +177,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
# + right replica column(s) # + right replica column(s)
column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0], column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
rows=self.row_size + self.extra_rows, rows=self.row_size + self.extra_rows,
mirror=(self.left_rbl + 1) %2) mirror=(self.rbl[0] + 1) %2)
self.add_mod(self.row_cap_right) self.add_mod(self.row_cap_right)
else: else:
# Dummy Row or Col Cap, depending on bitcell array properties # Dummy Row or Col Cap, depending on bitcell array properties