Merge remote-tracking branch 'private/dev' into control-logic-pull

.github/workflows/ci.yml

@@ -4,52 +4,54 @@ jobs:
   scn4me_subm:
     runs-on: self-hosted
     steps:
-      - name: Check out repository
+      - name: Checkout code
         uses: actions/checkout@v1
       - name: SCMOS test
         run: |
          . /home/github-runner/setup-paths.sh 
          export OPENRAM_HOME="`pwd`/compiler"
          export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech"
-         export OPENRAM_TMP="`pwd`/scn4me_subm"
+         export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm_temp"
-         python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t scn4m_subm
+         #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm
+         $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm
       - name: Archive
         if: ${{ failure() }}
         uses: actions/upload-artifact@v2
         with:
          name: scn4me_subm Archives
-         path: $OPENRAM_TMP/ 
+         path: ${{ github.workspace }}/scn4me_subm_temp/*/
   freepdk45:
     runs-on: self-hosted
     steps:
-      - name: Check out repository
+      - name: Checkout code
         uses: actions/checkout@v1
       - name: FreePDK45 test
         run: |
          . /home/github-runner/setup-paths.sh 
          export OPENRAM_HOME="`pwd`/compiler"
          export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech"
-         export OPENRAM_TMP="`pwd`/freepdk45"
+         export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp"
-         python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t freepdk45
+         #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45
+         $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45
       - name: Archive
         if: ${{ failure() }}
         uses: actions/upload-artifact@v2
         with:
          name: FreePDK45 Archives
-         path: $OPENRAM_TMP/ 
+         path: ${{ github.workspace }}/freepdk45_temp/*/
-  coverage:
+  # coverage_stats:
-    if: ${{ always() }}
+  #   if: ${{ always() }}
-    needs: [scn4me_subm, freepdk45]
+  #   needs: [scn4me_subm, freepdk45]
-    runs-on: self-hosted
+  #   runs-on: self-hosted
-    steps:
+  #   steps:
-      - name: Coverage stats
+  #     - name: Coverage stats
-        run: |
+  #       run: |
-         python3-coverage combine
+  #        python3-coverage combine
-         python3-coverage report
+  #        python3-coverage report
-         python3-coverage html -d coverage_html
+  #        python3-coverage html -d ${{ github.workspace }}/coverage_html
-      - name: Archive coverage
+  #     - name: Archive coverage
-        uses: actions/upload-artifact@v2
+  #       uses: actions/upload-artifact@v2
-        with:
+  #       with:
-         name: code-coverage-report
+  #        name: code-coverage-report
-         path: coverage_html/
+  #        path: ${{ github.workspace }}/coverage_html/
 

compiler/modules/sense_amp_array.py

@@ -146,10 +146,10 @@ class sense_amp_array(design.design):
             inst = self.local_insts[i]
 
             for gnd_pin in inst.get_pins("gnd"):
-                self.copy_power_pin(gnd_pin, directions=("V", "V"))
+                self.copy_power_pin(gnd_pin)
 
             for vdd_pin in inst.get_pins("vdd"):
-                self.copy_power_pin(vdd_pin, directions=("V", "V"))
+                self.copy_power_pin(vdd_pin)
 
             bl_pin = inst.get_pin(inst.mod.get_bl_names())
             br_pin = inst.get_pin(inst.mod.get_br_names())

compiler/router/direction.py

@@ -7,6 +7,8 @@
 #
 from enum import Enum
 from vector3d import vector3d
+import debug
+
 
 class direction(Enum):
     NORTH = 1
@@ -20,7 +22,6 @@ class direction(Enum):
     SOUTHEAST = 9
     SOUTHWEST = 10
 
-
     def get_offset(direct):
         """
         Returns the vector offset for a given direction.

compiler/router/pin_group.py

@@ -34,7 +34,6 @@ class pin_group:
         # Remove any redundant pins (i.e. contained in other pins)
         self.remove_redundant_pins()
 
-
         self.router = router
         # These are the corresponding pin grids for each pin group.
         self.grids = set()
@@ -101,13 +100,11 @@ class pin_group:
         if local_debug:
             debug.info(0, "INITIAL: {}".format(pin_list))
 
-        new_pin_list = pin_list.copy()
+        add_indices = set(range(len(pin_list)))
-
-        remove_indices = set()
         # This is n^2, but the number is small
         for index1, pin1 in enumerate(pin_list):
             # If we remove this pin, it can't contain other pins
-            if index1 in remove_indices:
+            if index1 not in add_indices:
                 continue
 
             for index2, pin2 in enumerate(pin_list):
@@ -117,17 +114,15 @@ class pin_group:
                 if index1 == index2:
                     continue
                 # If we already removed it, can't remove it again...
-                if index2 in remove_indices:
+                if index2 not in add_indices:
                     continue
 
                 if pin1.contains(pin2):
                     if local_debug:
                         debug.info(0, "{0} contains {1}".format(pin1, pin2))
-                    remove_indices.add(index2)
+                    add_indices.remove(index2)
 
-        # Remove them in decreasing order to not invalidate the indices
+        new_pin_list = [pin_list[x] for x in add_indices]
-        for i in sorted(remove_indices, reverse=True):
-            del new_pin_list[i]
 
         if local_debug:
             debug.info(0, "FINAL  : {}".format(new_pin_list))
@@ -423,13 +418,15 @@ class pin_group:
         # We may have started with an empty set
         debug.check(len(self.grids) > 0, "Cannot seed an grid empty set.")
 
+        common_blockages = self.router.get_blocked_grids() & self.grids
+        
         # Start with the ll and make the widest row
         row = [ll]
         # Move in dir1 while we can
         while True:
             next_cell = row[-1] + offset1
             # Can't move if not in the pin shape
-            if next_cell in self.grids and next_cell not in self.router.get_blocked_grids():
+            if next_cell in self.grids and next_cell not in common_blockages:
                 row.append(next_cell)
             else:
                 break
@@ -438,7 +435,7 @@ class pin_group:
             next_row = [x + offset2 for x in row]
             for cell in next_row:
                 # Can't move if any cell is not in the pin shape
-                if cell not in self.grids or cell in self.router.get_blocked_grids():
+                if cell not in self.grids or cell in common_blockages:
                     break
             else:
                 row = next_row
@@ -619,6 +616,11 @@ class pin_group:
         # Set of track adjacent to or paritally overlap a pin (not full DRC connection)
         partial_set = set()
 
+        # for pin in self.pins:
+        #     lx = pin.lx()
+        #     ly = pin.by()
+        #     if  lx > 87.9 and lx < 87.99 and ly > 18.56 and ly < 18.6:
+        #         breakpoint()
         for pin in self.pins:
             debug.info(4, "  Converting {0}".format(pin))
             # Determine which tracks the pin overlaps
@@ -632,7 +634,8 @@ class pin_group:
             blockage_in_tracks = self.router.convert_blockage(pin)
             # Must include the pins here too because these are computed in a different
             # way than blockages.
-            self.blockages.update(sufficient | insufficient | blockage_in_tracks)
+            blockages = sufficient | insufficient | blockage_in_tracks
+            self.blockages.update(blockages)
             
         # If we have a blockage, we must remove the grids
         # Remember, this excludes the pin blockages already

compiler/router/router.py

@@ -504,13 +504,20 @@ class router(router_tech):
             ll = vector(boundary[0], boundary[1])
             ur = vector(boundary[2], boundary[3])
             rect = [ll, ur]
-            new_pin = pin_layout("blockage{}".format(len(self.blockages)),
+            new_shape = pin_layout("blockage{}".format(len(self.blockages)),
                                    rect,
                                    lpp)
+            
             # If there is a rectangle that is the same in the pins,
             # it isn't a blockage!
-            if new_pin not in self.all_pins:
+            if new_shape not in self.all_pins and not self.pin_contains(new_shape):
-                self.blockages.append(new_pin)
+                self.blockages.append(new_shape)
+
+    def pin_contains(self, shape):
+        for pin in self.all_pins:
+            if pin.contains(shape):
+                return True
+        return False
         
     def convert_point_to_units(self, p):
         """
@@ -1048,6 +1055,7 @@ class router(router_tech):
         # Double check source and taget are not same node, if so, we are done!
         for k, v in self.rg.map.items():
             if v.source and v.target:
+                self.paths.append([k])
                 return True
 
         # returns the path in tracks

compiler/router/supply_tree_router.py

@@ -144,6 +144,7 @@ class supply_tree_router(router):
                 self.add_pin_component_source(pin_name, src_idx)
 
                 # Marks all pin components except index as target
+                # which unmarks it as a blockage too
                 self.add_pin_component_target(pin_name, dest_idx)
 
                 # Actually run the A* router

compiler/sram/sram_1bank.py

@@ -325,14 +325,14 @@ class sram_1bank(sram_base):
         # they might create some blockages
         self.add_layout_pins()
 
-        # Route the supplies first since the MST is not blockage aware
-        # and signals can route to anywhere on sides (it is flexible)
-        self.route_supplies()
-
         # Route the pins to the perimeter
         if OPTS.perimeter_pins:
             self.route_escape_pins()
             
+        # Route the supplies first since the MST is not blockage aware
+        # and signals can route to anywhere on sides (it is flexible)
+        self.route_supplies()
+        
     def route_dffs(self, add_routes=True):
 
         for port in self.all_ports: