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Fix single spare_wen naming

This commit is contained in:
mrg 2021-06-18 08:43:21 -07:00
parent 67877175b2
commit 1299989332
1 changed files with 26 additions and 13 deletions
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31
compiler/sram/sram_base.py
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@ -84,8 +84,11 @@ class sram_base(design, verilog, lef):
for port in self.write_ports: for port in self.write_ports:
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT") self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT")
for bit in range(self.num_spare_cols): if self.num_spare_cols == 1:
self.add_pin("spare_wen{0}[{1}]".format(port, bit), "INPUT") self.add_pin("spare_wen{0}".format(port), "INPUT")
else:
for bit in range(self.num_spare_cols):
self.add_pin("spare_wen{0}[{1}]".format(port, bit), "INPUT")
for port in self.read_ports: for port in self.read_ports:
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT") self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
@ -358,8 +361,11 @@ class sram_base(design, verilog, lef):
pins_to_route.append("wmask{0}[{1}]".format(port, bit)) pins_to_route.append("wmask{0}[{1}]".format(port, bit))
if port in self.write_ports: if port in self.write_ports:
for bit in range(self.num_spare_cols): if self.num_spare_cols == 1:
pins_to_route.append("spare_wen{0}[{1}]".format(port, bit)) pins_to_route.append("spare_wen{0}".format(port))
else:
for bit in range(self.num_spare_cols):
pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
from signal_escape_router import signal_escape_router as router from signal_escape_router import signal_escape_router as router
rtr=router(layers=self.m3_stack, rtr=router(layers=self.m3_stack,
@ -562,8 +568,11 @@ class sram_base(design, verilog, lef):
temp.append("w_en{0}".format(port)) temp.append("w_en{0}".format(port))
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
temp.append("bank_wmask{}[{}]".format(port, bit)) temp.append("bank_wmask{}[{}]".format(port, bit))
for bit in range(self.num_spare_cols): if self.num_spare_cols == 1:
temp.append("bank_spare_wen{0}[{1}]".format(port, bit)) temp.append("bank_spare_wen{0}".format(port))
else:
for bit in range(self.num_spare_cols):
temp.append("bank_spare_wen{0}_{1}".format(port, bit))
for port in self.all_ports: for port in self.all_ports:
temp.append("wl_en{0}".format(port)) temp.append("wl_en{0}".format(port))
temp.extend(self.ext_supplies) temp.extend(self.ext_supplies)
@ -695,9 +704,13 @@ class sram_base(design, verilog, lef):
# inputs, outputs/output/bar # inputs, outputs/output/bar
inputs = [] inputs = []
outputs = [] outputs = []
for bit in range(self.num_spare_cols): if self.num_spare_cols == 1:
inputs.append("spare_wen{}[{}]".format(port, bit)) inputs.append("spare_wen{}".format(port))
outputs.append("bank_spare_wen{}[{}]".format(port, bit)) outputs.append("bank_spare_wen{}".format(port))
else:
for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)