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Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell.

This commit is contained in:
mguthaus 2018-02-16 10:40:05 -08:00
parent cb449a1cd2
commit 1297cb4e40
3 changed files with 2 additions and 2 deletions
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2
compiler/modules/dff.py
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@ -10,7 +10,7 @@ class dff(design.design):
Memory address flip-flop Memory address flip-flop
""" """
pin_names = ["d", "clk", "q", "vdd", "gnd"] pin_names = ["d", "q", "clk", "vdd", "gnd"]
(width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"]) (width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"]) pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"])

BIN
technology/freepdk45/gds_lib/dff.gds
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2
technology/freepdk45/sp_lib/dff.sp
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@ -3,7 +3,7 @@
* Program "Calibre xRC" * Program "Calibre xRC"
* Version "v2007.2_34.24" * Version "v2007.2_34.24"
* *
.subckt dff d clk q vdd gnd .subckt dff d q clk vdd gnd
* *
MM21 q a_66_6# gnd gnd NMOS_VTG L=5e-08 W=5e-07 MM21 q a_66_6# gnd gnd NMOS_VTG L=5e-08 W=5e-07
MM19 a_76_6# a_2_6# a_66_6# gnd NMOS_VTG L=5e-08 W=2.5e-07 MM19 a_76_6# a_2_6# a_66_6# gnd NMOS_VTG L=5e-08 W=2.5e-07