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Add internal vdd/gnd connections for delay chain

This commit is contained in:
Matt Guthaus 2018-07-19 10:37:47 -07:00
parent 51958814a0
commit 128dfd5830
1 changed files with 19 additions and 13 deletions
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32
compiler/modules/delay_chain.py
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@ -166,20 +166,26 @@ class delay_chain(design.design):
# Add power and ground to all the cells except: # Add power and ground to all the cells except:
# the fanout driver, the right-most load # the fanout driver, the right-most load
# The routing to connect the loads is over the first and last cells # The routing to connect the loads is over the first and last cells
for pin_name in ["vdd", "gnd"]: # We have an even number of drivers and must only do every other
# We have an even number of drivers and must only do every other # supply rail
# supply rail for i in range(0,len(self.driver_inst_list),2):
for i in range(len(self.driver_inst_list),2): inv = self.driver_inst_list[i]
inv = self.driver_inst_list[i] for load in self.load_inst_map[inv]:
for load in self.load_inst_map[inv]: if load==self.rightest_load_inst[inv]:
if load in self.rightest_load_inst: continue
continue for pin_name in ["vdd", "gnd"]:
pin = load.get_pin(pin_name) pin = load.get_pin(pin_name)
self.add_power_pin(pin_name, pin.center()) self.add_power_pin(pin_name, pin.rc())
# self.add_rect(layer="metal1", else:
# offset=pin.ll(), # We have an even number of rows, so need to get the last gnd rail
# width=self.width, inv = self.driver_inst_list[-1]
# height=pin.height()) for load in self.load_inst_map[inv]:
if load==self.rightest_load_inst[inv]:
continue
pin_name = "gnd"
pin = load.get_pin(pin_name)
self.add_power_pin(pin_name, pin.rc())
# input is A pin of first inverter # input is A pin of first inverter
a_pin = self.driver_inst_list[0].get_pin("A") a_pin = self.driver_inst_list[0].get_pin("A")