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Enable riscv tests

This commit is contained in:
Matt Guthaus 2020-09-30 12:39:40 -07:00
parent f4e6a8895b
commit 112d57d90a
7 changed files with 47 additions and 53 deletions
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9
compiler/modules/bank.py
View File

@ -8,8 +8,8 @@
import debug
import design
from sram_factory import factory
from math import log, ceil, floor, sqrt
from tech import drc
from math import log, ceil, floor
from tech import drc, layer
from vector import vector
from globals import OPTS
@ -374,8 +374,6 @@ class bank(design.design):
port=port))
self.add_mod(self.port_address[port])
total_cols = self.num_cols + self.num_spare_cols
try:
local_array_size = OPTS.local_array_size
except AttributeError:
@ -383,6 +381,7 @@ class bank(design.design):
if local_array_size > 0:
# Find the even multiple that satisfies the fanout with equal sized local arrays
total_cols = self.num_cols + self.num_spare_cols
num_lb = floor(total_cols / local_array_size)
final_size = total_cols - num_lb * local_array_size
cols = [local_array_size] * (num_lb - 1)
@ -393,7 +392,7 @@ class bank(design.design):
rows=self.num_rows)
else:
self.bitcell_array = factory.create(module_type="replica_bitcell_array",
cols=total_cols,
cols=self.num_cols + self.num_spare_cols,
rows=self.num_rows)
self.add_mod(self.bitcell_array)

22
compiler/modules/write_driver_array.py
View File

@ -215,18 +215,20 @@ class write_driver_array(design.design):
start_layer=pin.layer)
if self.write_size:
for bit in range(self.num_wmasks):
first_inst = self.driver_insts[bit * self.write_size]
first_en_pin = first_inst.get_pin(first_inst.mod.en_name)
inst = self.driver_insts[bit * self.write_size]
en_pin = inst.get_pin(inst.mod.en_name)
# Determine width of wmask modified en_pin with/without col mux
wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
if (self.words_per_row == 1):
en_gap = self.driver_spacing - en_pin.width()
else:
en_gap = self.driver_spacing
last_inst = self.driver_insts[(bit + 1) * self.write_size - 1]
last_en_pin = last_inst.get_pin(last_inst.mod.en_name)
wmask_en_len = last_en_pin.rx() - first_en_pin.lx()
self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
layer=first_en_pin.layer,
offset=first_en_pin.ll(),
width=wmask_en_len,
height=first_en_pin.height())
layer=en_pin.layer,
offset=en_pin.ll(),
width=wmask_en_len - en_gap,
height=en_pin.height())
for i in range(self.num_spare_cols):
inst = self.driver_insts[self.word_size + i]

3
compiler/options.py
View File

@ -30,6 +30,9 @@ class options(optparse.Values):
num_r_ports = 0
num_w_ports = 0
# By default, use local arrays with a max fanout of 16
#local_array_size = 16
# Write mask size, default will be overwritten with word_size if not user specified
write_size = None

19
compiler/sram/sram_base.py
View File

@ -118,19 +118,8 @@ class sram_base(design, verilog, lef):
Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
OPTS.words_per_row = self.words_per_row
row = int(cell % (OPTS.num_words / self.words_per_row))
col = int(cell / (OPTS.num_words))
self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num,
row,
col,
storage_layer_name,
Q))
self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num,
row,
col,
storage_layer_name,
Q_bar))
self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))), storage_layer_name, Q_bar)
for cell in range(len(bl_offsets)):
col = bl_meta[cell][0][2]
@ -160,6 +149,10 @@ class sram_base(design, verilog, lef):
offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]]
self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), storage_layer_name, offset)
def create_netlist(self):
""" Netlist creation """

12
compiler/tests/50_riscv_func_test.py
View File

@ -15,28 +15,26 @@ from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 50_riscv_func_test")
class riscv_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
globals.setup_bitcell()
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.local_array_size = 16
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
globals.setup_bitcell()
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional
from characterizer import functional, delay
from sram_config import sram_config
c = sram_config(word_size=32,
write_size=8,

3
compiler/tests/50_riscv_phys_test.py
View File

@ -15,7 +15,6 @@ from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 50_riscv_phys_test")
class riscv_phys_test(openram_test):
@ -27,10 +26,10 @@ class riscv_phys_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
OPTS.local_array_size = 16
globals.setup_bitcell()
OPTS.route_supplies = False
OPTS.perimeter_pins = False
OPTS.local_array_size = 16
c = sram_config(word_size=32,
write_size=8,