luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Enable riscv tests

This commit is contained in:
Matt Guthaus 2020-09-30 12:39:40 -07:00
parent f4e6a8895b
commit 112d57d90a
7 changed files with 47 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
compiler/modules/bank.py
View File

@ -8,8 +8,8 @@
import debug import debug
import design import design
from sram_factory import factory from sram_factory import factory
from math import log, ceil, floor, sqrt from math import log, ceil, floor
from tech import drc from tech import drc, layer
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
@ -374,8 +374,6 @@ class bank(design.design):
port=port)) port=port))
self.add_mod(self.port_address[port]) self.add_mod(self.port_address[port])
total_cols = self.num_cols + self.num_spare_cols
try: try:
local_array_size = OPTS.local_array_size local_array_size = OPTS.local_array_size
except AttributeError: except AttributeError:
@ -383,6 +381,7 @@ class bank(design.design):
if local_array_size > 0: if local_array_size > 0:
# Find the even multiple that satisfies the fanout with equal sized local arrays # Find the even multiple that satisfies the fanout with equal sized local arrays
total_cols = self.num_cols + self.num_spare_cols
num_lb = floor(total_cols / local_array_size) num_lb = floor(total_cols / local_array_size)
final_size = total_cols - num_lb * local_array_size final_size = total_cols - num_lb * local_array_size
cols = [local_array_size] * (num_lb - 1) cols = [local_array_size] * (num_lb - 1)
@ -393,7 +392,7 @@ class bank(design.design):
rows=self.num_rows) rows=self.num_rows)
else: else:
self.bitcell_array = factory.create(module_type="replica_bitcell_array", self.bitcell_array = factory.create(module_type="replica_bitcell_array",
cols=total_cols, cols=self.num_cols + self.num_spare_cols,
rows=self.num_rows) rows=self.num_rows)
self.add_mod(self.bitcell_array) self.add_mod(self.bitcell_array)

24
compiler/modules/write_driver_array.py
View File

@ -215,25 +215,27 @@ class write_driver_array(design.design):
start_layer=pin.layer) start_layer=pin.layer)
if self.write_size: if self.write_size:
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
first_inst = self.driver_insts[bit * self.write_size] inst = self.driver_insts[bit * self.write_size]
first_en_pin = first_inst.get_pin(first_inst.mod.en_name) en_pin = inst.get_pin(inst.mod.en_name)
# Determine width of wmask modified en_pin with/without col mux
wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
if (self.words_per_row == 1):
en_gap = self.driver_spacing - en_pin.width()
else:
en_gap = self.driver_spacing
last_inst = self.driver_insts[(bit + 1) * self.write_size - 1]
last_en_pin = last_inst.get_pin(last_inst.mod.en_name)
wmask_en_len = last_en_pin.rx() - first_en_pin.lx()
self.add_layout_pin(text=self.en_name + "_{0}".format(bit), self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
layer=first_en_pin.layer, layer=en_pin.layer,
offset=first_en_pin.ll(), offset=en_pin.ll(),
width=wmask_en_len, width=wmask_en_len - en_gap,
height=first_en_pin.height()) height=en_pin.height())
for i in range(self.num_spare_cols): for i in range(self.num_spare_cols):
inst = self.driver_insts[self.word_size + i] inst = self.driver_insts[self.word_size + i]
en_pin = inst.get_pin(inst.mod.en_name) en_pin = inst.get_pin(inst.mod.en_name)
self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks), self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks),
layer="m1", layer="m1",
offset=en_pin.lr() + vector(-drc("minwidth_m1"), 0)) offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
elif self.num_spare_cols and not self.write_size: elif self.num_spare_cols and not self.write_size:
# shorten enable rail to accomodate those for spare write drivers # shorten enable rail to accomodate those for spare write drivers

3
compiler/options.py
View File

@ -30,6 +30,9 @@ class options(optparse.Values):
num_r_ports = 0 num_r_ports = 0
num_w_ports = 0 num_w_ports = 0
# By default, use local arrays with a max fanout of 16
#local_array_size = 16
# Write mask size, default will be overwritten with word_size if not user specified # Write mask size, default will be overwritten with word_size if not user specified
write_size = None write_size = None

35
compiler/sram/sram_base.py
View File

@ -87,8 +87,8 @@ class sram_base(design, verilog, lef):
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT") self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
self.add_pin("vdd", "POWER") self.add_pin("vdd","POWER")
self.add_pin("gnd", "GROUND") self.add_pin("gnd","GROUND")
def add_global_pex_labels(self): def add_global_pex_labels(self):
""" """
@ -118,19 +118,8 @@ class sram_base(design, verilog, lef):
Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]] Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]] Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
OPTS.words_per_row = self.words_per_row OPTS.words_per_row = self.words_per_row
row = int(cell % (OPTS.num_words / self.words_per_row)) self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))) , storage_layer_name, Q)
col = int(cell / (OPTS.num_words)) self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))), storage_layer_name, Q_bar)
self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num,
row,
col,
storage_layer_name,
Q))
self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num,
row,
col,
storage_layer_name,
Q_bar))
for cell in range(len(bl_offsets)): for cell in range(len(bl_offsets)):
col = bl_meta[cell][0][2] col = bl_meta[cell][0][2]
@ -142,23 +131,27 @@ class sram_base(design, verilog, lef):
col = br_meta[cell][0][2] col = br_meta[cell][0][2]
for bitline in range(len(br_offsets[cell])): for bitline in range(len(br_offsets[cell])):
bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]] bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]]
br.append([bitline_location, br_meta[cell][bitline][3], col]) br.append([bitline_location, br_meta[cell][bitline][3], col])
for i in range(len(bl)): for i in range(len(bl)):
self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0]) self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0])
for i in range(len(br)): for i in range(len(br)):
self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0]) self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0])
# add pex labels for control logic # add pex labels for control logic
for i in range(len(self.control_logic_insts)): for i in range (len(self.control_logic_insts)):
instance = self.control_logic_insts[i] instance = self.control_logic_insts[i]
control_logic_offset = instance.offset control_logic_offset = instance.offset
for output in instance.mod.output_list: for output in instance.mod.output_list:
pin = instance.mod.get_pin(output) pin = instance.mod.get_pin(output)
pin.transform([0, 0], instance.mirror, instance.rotate) pin.transform([0,0], instance.mirror, instance.rotate)
offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]] offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]]
self.add_layout_pin_rect_center("{0}{1}".format(pin.name, i), storage_layer_name, offset) self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), storage_layer_name, offset)
def create_netlist(self): def create_netlist(self):
""" Netlist creation """ """ Netlist creation """

2
compiler/sram/sram_config.py
View File

@ -25,7 +25,7 @@ class sram_config:
# This will get over-written when we determine the organization # This will get over-written when we determine the organization
self.words_per_row = words_per_row self.words_per_row = words_per_row
self.compute_sizes() self.compute_sizes()
def set_local_config(self, module): def set_local_config(self, module):
""" Copy all of the member variables to the given module for convenience """ """ Copy all of the member variables to the given module for convenience """

18
compiler/tests/50_riscv_func_test.py
View File

@ -8,35 +8,33 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys,os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 50_riscv_func_test")
# @unittest.skip("SKIPPING 50_riscv_func_test")
class riscv_func_test(openram_test): class riscv_func_test(openram_test):
def runTest(self): def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file) globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
globals.setup_bitcell()
OPTS.analytical_delay = False OPTS.analytical_delay = False
OPTS.netlist_only = True OPTS.netlist_only = True
OPTS.trim_netlist = False OPTS.trim_netlist = False
OPTS.local_array_size = 16 OPTS.local_array_size = 16
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
globals.setup_bitcell()
# This is a hack to reload the characterizer __init__ with the spice version # This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload from importlib import reload
import characterizer import characterizer
reload(characterizer) reload(characterizer)
from characterizer import functional from characterizer import functional, delay
from sram_config import sram_config from sram_config import sram_config
c = sram_config(word_size=32, c = sram_config(word_size=32,
write_size=8, write_size=8,
@ -56,7 +54,7 @@ class riscv_func_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner) f = functional(s.s, tempspice, corner)
(fail, error) = f.run() (fail, error) = f.run()
self.assertTrue(fail, error) self.assertTrue(fail,error)
globals.end_openram() globals.end_openram()

9
compiler/tests/50_riscv_phys_test.py
View File

@ -8,15 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys,os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 50_riscv_phys_test")
# @unittest.skip("SKIPPING 50_riscv_phys_test")
class riscv_phys_test(openram_test): class riscv_phys_test(openram_test):
def runTest(self): def runTest(self):
@ -27,11 +26,11 @@ class riscv_phys_test(openram_test):
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
OPTS.local_array_size = 16
globals.setup_bitcell() globals.setup_bitcell()
OPTS.route_supplies = False OPTS.route_supplies = False
OPTS.perimeter_pins = False OPTS.perimeter_pins = False
OPTS.local_array_size = 16
c = sram_config(word_size=32, c = sram_config(word_size=32,
write_size=8, write_size=8,
num_words=256, num_words=256,