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PEP8 cleanup

This commit is contained in:
mrg 2020-04-21 15:36:38 -07:00
parent fc85dfe29f
commit 0f6998a1c5
1 changed files with 33 additions and 39 deletions
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72
compiler/modules/delay_chain.py
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@ -7,12 +7,11 @@
# #
import debug import debug
import design import design
from tech import drc
from contact import contact
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
class delay_chain(design.design): class delay_chain(design.design):
""" """
Generate a delay chain with the given number of stages and fanout. Generate a delay chain with the given number of stages and fanout.
@ -28,7 +27,7 @@ class delay_chain(design.design):
# Two fanouts are needed so that we can route the vdd/gnd connections # Two fanouts are needed so that we can route the vdd/gnd connections
for f in fanout_list: for f in fanout_list:
debug.check(f>=2,"Must have >=2 fanouts for each stage.") debug.check(f>=2, "Must have >=2 fanouts for each stage.")
# number of inverters including any fanout loads. # number of inverters including any fanout loads.
self.fanout_list = fanout_list self.fanout_list = fanout_list
@ -36,7 +35,6 @@ class delay_chain(design.design):
self.create_netlist() self.create_netlist()
if not OPTS.netlist_only: if not OPTS.netlist_only:
self.create_layout() self.create_layout()
def create_netlist(self): def create_netlist(self):
self.add_modules() self.add_modules()
@ -45,9 +43,9 @@ class delay_chain(design.design):
def create_layout(self): def create_layout(self):
# Each stage is a a row # Each stage is a a row
self.height = len(self.fanout_list)*self.inv.height self.height = len(self.fanout_list) * self.inv.height
# The width is determined by the largest fanout plus the driver # The width is determined by the largest fanout plus the driver
self.width = (max(self.fanout_list)+1) * self.inv.width self.width = (max(self.fanout_list) + 1) * self.inv.width
self.place_inverters() self.place_inverters()
self.route_inverters() self.route_inverters()
@ -71,7 +69,7 @@ class delay_chain(design.design):
self.driver_inst_list = [] self.driver_inst_list = []
self.rightest_load_inst = {} self.rightest_load_inst = {}
self.load_inst_map = {} self.load_inst_map = {}
for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list): for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list):
# Add the inverter # Add the inverter
cur_driver=self.add_inst(name="dinv{}".format(stage_num), cur_driver=self.add_inst(name="dinv{}".format(stage_num),
mod=self.inv) mod=self.inv)
@ -79,23 +77,23 @@ class delay_chain(design.design):
self.driver_inst_list.append(cur_driver) self.driver_inst_list.append(cur_driver)
# Hook up the driver # Hook up the driver
if stage_num+1==len(self.fanout_list): if stage_num + 1 == len(self.fanout_list):
stageout_name = "out" stageout_name = "out"
else: else:
stageout_name = "dout_{}".format(stage_num+1) stageout_name = "dout_{}".format(stage_num + 1)
if stage_num == 0: if stage_num == 0:
stagein_name = "in" stagein_name = "in"
else: else:
stagein_name = "dout_{}".format(stage_num) stagein_name = "dout_{}".format(stage_num)
self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"]) self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"])
# Now add the dummy loads to the right # Now add the dummy loads to the right
self.load_inst_map[cur_driver]=[] self.load_inst_map[cur_driver]=[]
for i in range(fanout_size): for i in range(fanout_size):
cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num,i), cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num, i),
mod=self.inv) mod=self.inv)
# Fanout stage is always driven by driver and output is disconnected # Fanout stage is always driven by driver and output is disconnected
disconnect_name = "n_{0}_{1}".format(stage_num,i) disconnect_name = "n_{0}_{1}".format(stage_num, i)
self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"]) self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"])
# Keep track of all the loads to connect their inputs as a load # Keep track of all the loads to connect their inputs as a load
@ -106,13 +104,13 @@ class delay_chain(design.design):
def place_inverters(self): def place_inverters(self):
""" Place the inverters and connect them based on the stage list """ """ Place the inverters and connect them based on the stage list """
for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list): for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list):
if stage_num % 2: if stage_num % 2:
inv_mirror = "MX" inv_mirror = "MX"
inv_offset = vector(0, (stage_num+1)* self.inv.height) inv_offset = vector(0, (stage_num + 1) * self.inv.height)
else: else:
inv_mirror = "R0" inv_mirror = "R0"
inv_offset = vector(0, stage_num * self.inv.height) inv_offset = vector(0, stage_num * self.inv.height)
# Add the inverter # Add the inverter
cur_driver=self.driver_inst_list[stage_num] cur_driver=self.driver_inst_list[stage_num]
@ -122,10 +120,9 @@ class delay_chain(design.design):
# Now add the dummy loads to the right # Now add the dummy loads to the right
load_list = self.load_inst_map[cur_driver] load_list = self.load_inst_map[cur_driver]
for i in range(fanout_size): for i in range(fanout_size):
inv_offset += vector(self.inv.width,0) inv_offset += vector(self.inv.width, 0)
load_list[i].place(offset=inv_offset, load_list[i].place(offset=inv_offset,
mirror=inv_mirror) mirror=inv_mirror)
def add_route(self, pin1, pin2): def add_route(self, pin1, pin2):
""" This guarantees that we route from the top to bottom row correctly. """ """ This guarantees that we route from the top to bottom row correctly. """
@ -134,9 +131,9 @@ class delay_chain(design.design):
if pin1_pos.y == pin2_pos.y: if pin1_pos.y == pin2_pos.y:
self.add_path("m2", [pin1_pos, pin2_pos]) self.add_path("m2", [pin1_pos, pin2_pos])
else: else:
mid_point = vector(pin2_pos.x, 0.5*(pin1_pos.y+pin2_pos.y)) mid_point = vector(pin2_pos.x, 0.5 * (pin1_pos.y + pin2_pos.y))
# Written this way to guarantee it goes right first if we are switching rows # Written this way to guarantee it goes right first if we are switching rows
self.add_path("m2", [pin1_pos, vector(pin1_pos.x,mid_point.y), mid_point, vector(mid_point.x,pin2_pos.y), pin2_pos]) self.add_path("m2", [pin1_pos, vector(pin1_pos.x, mid_point.y), mid_point, vector(mid_point.x, pin2_pos.y), pin2_pos])
def route_inverters(self): def route_inverters(self):
""" Add metal routing for each of the fanout stages """ """ Add metal routing for each of the fanout stages """
@ -145,7 +142,7 @@ class delay_chain(design.design):
inv = self.driver_inst_list[i] inv = self.driver_inst_list[i]
for load in self.load_inst_map[inv]: for load in self.load_inst_map[inv]:
# Drop a via on each A pin # Drop a via on each A pin
a_pin = load.get_pin("A") a_pin = load.get_pin("A")
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=a_pin.center()) offset=a_pin.center())
self.add_via_center(layers=self.m2_stack, self.add_via_center(layers=self.m2_stack,
@ -161,19 +158,17 @@ class delay_chain(design.design):
offset=z_pin.center()) offset=z_pin.center())
self.add_via_center(layers=self.m2_stack, self.add_via_center(layers=self.m2_stack,
offset=z_pin.center()) offset=z_pin.center())
self.add_path("m3",[z_pin.center(), a_max.center()]) self.add_path("m3", [z_pin.center(), a_max.center()])
# Route Z to the A of the next stage # Route Z to the A of the next stage
if i+1 < len(self.driver_inst_list): if i + 1 < len(self.driver_inst_list):
z_pin = inv.get_pin("Z") z_pin = inv.get_pin("Z")
next_inv = self.driver_inst_list[i+1] next_inv = self.driver_inst_list[i + 1]
next_a_pin = next_inv.get_pin("A") next_a_pin = next_inv.get_pin("A")
y_mid = (z_pin.cy() + next_a_pin.cy())/2 y_mid = (z_pin.cy() + next_a_pin.cy()) / 2
mid1_point = vector(z_pin.cx(), y_mid) mid1_point = vector(z_pin.cx(), y_mid)
mid2_point = vector(next_a_pin.cx(), y_mid) mid2_point = vector(next_a_pin.cx(), y_mid)
self.add_path("m2",[z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()])
def add_layout_pins(self): def add_layout_pins(self):
""" Add vdd and gnd rails and the input/output. Connect the gnd rails internally on """ Add vdd and gnd rails and the input/output. Connect the gnd rails internally on
@ -184,7 +179,7 @@ class delay_chain(design.design):
# The routing to connect the loads is over the first and last cells # The routing to connect the loads is over the first and last cells
# We have an even number of drivers and must only do every other # We have an even number of drivers and must only do every other
# supply rail # supply rail
for i in range(0,len(self.driver_inst_list),2): for i in range(0, len(self.driver_inst_list), 2):
inv = self.driver_inst_list[i] inv = self.driver_inst_list[i]
for load in self.load_inst_map[inv]: for load in self.load_inst_map[inv]:
if load==self.rightest_load_inst[inv]: if load==self.rightest_load_inst[inv]:
@ -202,43 +197,42 @@ class delay_chain(design.design):
pin = load.get_pin(pin_name) pin = load.get_pin(pin_name)
self.add_power_pin(pin_name, pin.rc()) self.add_power_pin(pin_name, pin.rc())
# input is A pin of first inverter # input is A pin of first inverter
a_pin = self.driver_inst_list[0].get_pin("A") a_pin = self.driver_inst_list[0].get_pin("A")
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=a_pin.center()) offset=a_pin.center())
self.add_layout_pin(text="in", self.add_layout_pin(text="in",
layer="m2", layer="m2",
offset=a_pin.ll().scale(1,0), offset=a_pin.ll().scale(1, 0),
height=a_pin.cy()) height=a_pin.cy())
# output is A pin of last load inverter # output is A pin of last load inverter
last_driver_inst = self.driver_inst_list[-1] last_driver_inst = self.driver_inst_list[-1]
a_pin = self.rightest_load_inst[last_driver_inst].get_pin("A") a_pin = self.rightest_load_inst[last_driver_inst].get_pin("A")
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=a_pin.center()) offset=a_pin.center())
mid_point = vector(a_pin.cx()+3*self.m2_width,a_pin.cy()) mid_point = vector(a_pin.cx() + 3 * self.m2_width, a_pin.cy())
self.add_path("m2",[a_pin.center(), mid_point, mid_point.scale(1,0)]) self.add_path("m2", [a_pin.center(), mid_point, mid_point.scale(1, 0)])
self.add_layout_pin_segment_center(text="out", self.add_layout_pin_segment_center(text="out",
layer="m2", layer="m2",
start=mid_point, start=mid_point,
end=mid_point.scale(1,0)) end=mid_point.scale(1, 0))
def get_cin(self): def get_cin(self):
"""Get the enable input ralative capacitance""" """Get the enable input ralative capacitance"""
#Only 1 input to the delay chain which is connected to an inverter. # Only 1 input to the delay chain which is connected to an inverter.
dc_cin = self.inv.get_cin() dc_cin = self.inv.get_cin()
return dc_cin return dc_cin
def determine_delayed_en_stage_efforts(self, ext_delayed_en_cout, inp_is_rise=True): def determine_delayed_en_stage_efforts(self, ext_delayed_en_cout, inp_is_rise=True):
"""Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load.""" """Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load."""
stage_effort_list = [] stage_effort_list = []
#Add a stage to the list for every stage in delay chain. Stages only differ in fanout except the last which has an external cout. # Add a stage to the list for every stage in delay chain.
# Stages only differ in fanout except the last which has an external cout.
last_stage_is_rise = inp_is_rise last_stage_is_rise = inp_is_rise
for stage_fanout in self.fanout_list: for stage_fanout in self.fanout_list:
stage_cout = self.inv.get_cin()*(stage_fanout+1) stage_cout = self.inv.get_cin() * (stage_fanout + 1)
if len(stage_effort_list) == len(self.fanout_list)-1: #last stage if len(stage_effort_list) == len(self.fanout_list) - 1:
stage_cout+=ext_delayed_en_cout stage_cout+=ext_delayed_en_cout
stage = self.inv.get_stage_effort(stage_cout, last_stage_is_rise) stage = self.inv.get_stage_effort(stage_cout, last_stage_is_rise)
stage_effort_list.append(stage) stage_effort_list.append(stage)