mirror of https://github.com/VLSIDA/OpenRAM.git
Remove write_driver_array.py.orig
this was the remainder of applying a diff using "patch". To avoid this mistake, add the filetypes created by "patch" to the .gitignore. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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Bastian Koppelmann
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da4c69ab98
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.DS_Store
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.DS_Store
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*~
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*~
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*.orig
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*.rej
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*.pyc
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*.pyc
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*.aux
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*.aux
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*.out
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*.out
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@ -1,202 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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from tech import drc
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import debug
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class write_driver_array(design.design):
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"""
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Array of tristate drivers to write to the bitlines through the column mux.
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Dynamically generated write driver array of all bitlines.
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"""
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def __init__(self, name, columns, word_size,write_size=None):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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self.add_comment("word_size {0}".format(word_size))
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self.columns = columns
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self.word_size = word_size
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self.write_size = write_size
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self.words_per_row = int(columns / word_size)
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if self.write_size:
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self.num_wmasks = int(self.word_size/self.write_size)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def get_bl_name(self):
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bl_name = self.driver.get_bl_names()
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return bl_name
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def get_br_name(self):
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br_name = self.driver.get_br_names()
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return br_name
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@property
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def data_name(self):
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return "data"
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@property
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def en_name(self):
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return "en"
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_write_array()
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def create_layout(self):
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if self.bitcell.width > self.driver.width:
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self.width = self.columns * self.bitcell.width
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else:
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self.width = self.columns * self.driver.width
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self.height = self.driver.height
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self.place_write_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(self.word_size):
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self.add_pin(self.data_name + "_{0}".format(i), "INPUT")
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for i in range(self.word_size):
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self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT")
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self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT")
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if self.write_size:
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for i in range(self.num_wmasks):
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self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
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else:
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self.add_pin(self.en_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.driver = factory.create(module_type="write_driver")
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self.add_mod(self.driver)
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# This is just used for measurements,
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# so don't add the module
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self.bitcell = factory.create(module_type="bitcell")
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def create_write_array(self):
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self.driver_insts = {}
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w = 0
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windex=0
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for i in range(0,self.columns,self.words_per_row):
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name = "write_driver{}".format(i)
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index = int(i/self.words_per_row)
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self.driver_insts[index]=self.add_inst(name=name,
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mod=self.driver)
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if self.write_size:
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self.connect_inst([self.data_name + "_{0}".format(index),
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self.get_bl_name() + "_{0}".format(index),
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self.get_br_name() + "_{0}".format(index),
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self.en_name + "_{0}".format(windex), "vdd", "gnd"])
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w+=1
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# when w equals write size, the next en pin can be connected since we are now at the next wmask bit
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if w == self.write_size:
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w = 0
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windex+=1
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else:
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self.connect_inst([self.data_name + "_{0}".format(index),
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self.get_bl_name() + "_{0}".format(index),
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self.get_br_name() + "_{0}".format(index),
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self.en_name, "vdd", "gnd"])
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def place_write_array(self):
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from tech import cell_properties
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if self.bitcell.width > self.driver.width:
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self.driver_spacing = self.bitcell.width
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else:
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self.driver_spacing = self.driver.width
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for i in range(0,self.columns,self.words_per_row):
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index = int(i/self.words_per_row)
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xoffset = i * self.driver_spacing
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if cell_properties.bitcell.mirror.y and i % 2:
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mirror = "MY"
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xoffset = xoffset + self.driver.width
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else:
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mirror = ""
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base = vector(xoffset, 0)
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self.driver_insts[index].place(offset=base, mirror=mirror)
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def add_layout_pins(self):
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for i in range(self.word_size):
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inst = self.driver_insts[i]
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din_pin = inst.get_pin(inst.mod.din_name)
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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layer="m2",
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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layer="m2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=bl_pin.height())
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br_pin = inst.get_pin(inst.mod.get_br_names())
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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layer="m2",
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=br_pin.height())
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for n in ["vdd", "gnd"]:
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pin_list = self.driver_insts[i].get_pins(n)
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for pin in pin_list:
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self.add_power_pin(name = n,
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loc = pin.center(),
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vertical=True,
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start_layer = "m2")
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if self.write_size:
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for bit in range(self.num_wmasks):
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inst = self.driver_insts[bit*self.write_size]
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en_pin = inst.get_pin(inst.mod.en_name)
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# Determine width of wmask modified en_pin with/without col mux
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wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing)
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if (self.words_per_row == 1):
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en_gap = self.driver_spacing - en_pin.width()
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else:
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en_gap = self.driver_spacing
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self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
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layer=en_pin.layer,
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offset=en_pin.ll(),
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width=wmask_en_len-en_gap,
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height=en_pin.height())
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else:
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inst = self.driver_insts[0]
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self.add_layout_pin(text=self.en_name,
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layer="m1",
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offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1),
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width=self.width)
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def get_w_en_cin(self):
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"""Get the relative capacitance of all the enable connections in the bank"""
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#The enable is connected to a nand2 for every row.
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return self.driver.get_w_en_cin() * len(self.driver_insts)
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