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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
All modules have split netlist/layout.
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@@ -27,14 +27,17 @@ class tri_gate_array(design.design):
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self.width = (self.columns / self.words_per_row) * self.tri.width
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self.height = self.tri.height
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self.create_netlist()
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self.create_layout()
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self.DRC_LVS()
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def create_layout(self):
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"""generate layout """
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def create_netlist(self):
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self.add_pins()
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self.create_array()
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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"""create the name of pins depend on the word size"""
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@@ -50,15 +53,21 @@ class tri_gate_array(design.design):
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self.tri_inst = {}
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for i in range(0,self.columns,self.words_per_row):
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name = "Xtri_gate{0}".format(i)
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base = vector(i*self.tri.width, 0)
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self.tri_inst[i]=self.add_inst(name=name,
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mod=self.tri,
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offset=base)
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mod=self.tri)
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index = int(i/self.words_per_row)
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self.connect_inst(["in[{0}]".format(index),
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"out[{0}]".format(index),
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"en", "en_bar", "vdd", "gnd"])
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def place_array(self):
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""" Place the tri gate to the array """
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for i in range(0,self.columns,self.words_per_row):
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name = "Xtri_gate{0}".format(i)
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base = vector(i*self.tri.width, 0)
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self.place_inst(name=name,
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offset=base)
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def add_layout_pins(self):
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