Shortened write driver enable pin so that a write mask can be used without a col mux in layout.

compiler/modules/write_driver_array.py

@@ -113,7 +113,6 @@ class write_driver_array(design.design):
         for i in range(0,self.columns,self.words_per_row):
             index = int(i/self.words_per_row)
             base = vector(i * driver_spacing, 0)
-
             self.driver_insts[index].place(base)
 
             
@@ -152,11 +151,14 @@ class write_driver_array(design.design):
         if self.write_size is not None:
             for bit in range(self.num_wmasks):
                 en_pin = self.driver_insts[bit*self.write_size].get_pin("en")
+                # modifier to stretch enable pin for column mux
+                modifier = (self.words_per_row-1) + 0.65
                 self.add_layout_pin(text="en_{0}".format(bit),
                                     layer=en_pin.layer,
                                     offset=en_pin.ll(),
-                                    width=1.75*self.write_size*en_pin.width(),
+                                    width=modifier*self.write_size*en_pin.width(),
                                     height=en_pin.height())
+        else:
             self.add_layout_pin(text="en",
                                 layer="metal1",
                                 offset=self.driver_insts[0].get_pin("en").ll().scale(0,1),

compiler/tests/10_write_driver_array_wmask_test.py

@@ -0,0 +1,57 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class write_driver_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
+
+        # check write driver array for single port
+        debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=2")
+        a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=2)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4")
+        a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
+        self.local_check(a)
+
+        # check write driver array for multi-port
+        # OPTS.bitcell = "pbitcell"
+        # OPTS.num_rw_ports = 1
+        # OPTS.num_w_ports = 0
+        # OPTS.num_r_ports = 0
+        #
+        # factory.reset()
+        # debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
+        # a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
+        # self.local_check(a)
+        #
+        # debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
+        # a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
+        # self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

technology/scn4m_subm/mag_lib/write_driver.mag

@@ -1,6 +1,6 @@
 magic
 tech scmos
-timestamp 1564675126
+timestamp 1565289461
 << nwell >>
 rect -3 101 37 138
 rect -3 0 37 51
@@ -178,7 +178,7 @@ rect 3 35 7 38
 rect 19 35 23 38
 rect 7 31 19 35
 rect 0 24 7 28
-rect 11 24 36 28
+rect 11 24 31 28
 << m2contact >>
 rect 10 193 14 197
 rect 20 190 24 194