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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 19:49:33 +02:00
Remove add_mod and add module whenever calling add_inst.
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@@ -29,7 +29,7 @@ class port_data(design.design):
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self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
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else:
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self.num_wmasks = 0
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if num_spare_cols is not None:
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self.num_spare_cols = num_spare_cols + self.num_spare_cols
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if self.num_spare_cols is None:
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@@ -215,7 +215,6 @@ class port_data(design.design):
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port],
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column_offset=self.port - 1)
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self.add_mod(self.precharge_array)
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if self.port in self.read_ports:
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# RBLs don't get a sense amp
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@@ -224,7 +223,6 @@ class port_data(design.design):
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offsets=self.bit_offsets,
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words_per_row=self.words_per_row,
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num_spare_cols=self.num_spare_cols)
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self.add_mod(self.sense_amp_array)
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else:
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self.sense_amp_array = None
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@@ -236,7 +234,6 @@ class port_data(design.design):
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offsets=self.bit_offsets,
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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self.add_mod(self.column_mux_array)
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else:
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self.column_mux_array = None
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@@ -248,7 +245,6 @@ class port_data(design.design):
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offsets=self.bit_offsets,
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write_size=self.write_size,
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num_spare_cols=self.num_spare_cols)
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self.add_mod(self.write_driver_array)
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if self.write_size is not None:
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# RBLs don't get a write mask
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self.write_mask_and_array = factory.create(module_type="write_mask_and_array",
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@@ -256,7 +252,6 @@ class port_data(design.design):
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offsets=self.bit_offsets,
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word_size=self.word_size,
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write_size=self.write_size)
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self.add_mod(self.write_mask_and_array)
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else:
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self.write_mask_and_array = None
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@@ -858,10 +853,10 @@ class port_data(design.design):
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"""
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if self.column_mux_array:
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self.column_mux_array.graph_exclude_columns(column_include_num)
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def graph_clear_column_mux(self):
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"""
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Clear mux exclusions to allow different bit tests.
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"""
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if self.column_mux_array:
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self.column_mux_array.init_graph_params()
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self.column_mux_array.init_graph_params()
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