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Remove add_mod and add module whenever calling add_inst.

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This commit is contained in:
mrg
2021-11-22 11:33:27 -08:00
parent b94dd79125
commit 0c3ee643ab
58 changed files with 78 additions and 268 deletions
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compiler/bitcells/dummy_pbitcell.py
-1
View File
@@ -56,7 +56,6 @@ class dummy_pbitcell(design.design):
def add_modules(self):
self.prbc = factory.create(module_type="pbitcell",
dummy_bitcell=True)
self.add_mod(self.prbc)
self.height = self.prbc.height
self.width = self.prbc.width
compiler/bitcells/pbitcell.py
-5
View File
@@ -179,26 +179,21 @@ class pbitcell(bitcell_base.bitcell_base):
# create ptx for inverter transistors
self.inverter_nmos = ptx(width=inverter_nmos_width,
tx_type="nmos")
self.add_mod(self.inverter_nmos)
self.inverter_pmos = ptx(width=inverter_pmos_width,
tx_type="pmos")
self.add_mod(self.inverter_pmos)
# create ptx for readwrite transitors
self.readwrite_nmos = ptx(width=readwrite_nmos_width,
tx_type="nmos")
self.add_mod(self.readwrite_nmos)
# create ptx for write transitors
self.write_nmos = ptx(width=write_nmos_width,
tx_type="nmos")
self.add_mod(self.write_nmos)
# create ptx for read transistors
self.read_nmos = ptx(width=read_nmos_width,
tx_type="nmos")
self.add_mod(self.read_nmos)
def calculate_spacing(self):
""" Calculate transistor spacings """
compiler/bitcells/replica_pbitcell.py
-2
View File
@@ -58,7 +58,6 @@ class replica_pbitcell(design.design):
def add_modules(self):
self.prbc = factory.create(module_type="pbitcell",
replica_bitcell=True)
self.add_mod(self.prbc)
self.height = self.prbc.height
self.width = self.prbc.width
@@ -88,4 +87,3 @@ class replica_pbitcell(design.design):
self.copy_layout_pin(self.prbc_inst, "wl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "vdd")
self.copy_layout_pin(self.prbc_inst, "gnd")