mirror of https://github.com/VLSIDA/OpenRAM.git
Revert to 5V example until we fix spice models in scn4m_subm
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@ -3,7 +3,7 @@ num_words = 16
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tech_name = "scn4m_subm"
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tech_name = "scn4m_subm"
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process_corners = ["TT"]
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process_corners = ["TT"]
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supply_voltages = [ 3.3 ]
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supply_voltages = [5.0]
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temperatures = [25]
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temperatures = [25]
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output_path = "temp"
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output_path = "temp"
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