Reference local sram instance in sram.py.

compiler/sram.py

@@ -25,28 +25,30 @@ class sram():
 
         if num_banks == 1:
             from sram_1bank import sram_1bank
-            sram=sram_1bank(word_size, num_words, name)
+            self.s=sram_1bank(word_size, num_words, name)
         elif num_banks == 2:
             from sram_2bank import sram_2bank
-            sram=sram_2bank(word_size, num_words, name)            
+            self.s=sram_2bank(word_size, num_words, name)            
         elif num_banks == 4:
             from sram_4bank import sram_4bank
-            sram=sram_4bank(word_size, num_words, name)                        
+            self.s=sram_4bank(word_size, num_words, name)                        
         else:
             debug.error("Invalid number of banks.",-1)
 
-        sram.compute_sizes()
+        self.s.compute_sizes()
-        sram.create_modules()
+        self.s.create_modules()
-        sram.add_pins()
+        self.s.add_pins()
-        sram.create_layout()
+        self.s.create_layout()
         
         # Can remove the following, but it helps for debug!
-        sram.add_lvs_correspondence_points()
+        self.s.add_lvs_correspondence_points()
         
-        sram.offset_all_coordinates()
+        self.s.offset_all_coordinates()
-        (sram.width, sram.height) = sram.find_highest_coords()
+        highest_coord = self.s.find_highest_coords()
+        self.s.width = highest_coord[0]
+        self.s.height = highest_coord[1]
         
-        sram.DRC_LVS(final_verification=True)
+        self.s.DRC_LVS(final_verification=True)
 
         if not OPTS.is_unit_test:
             print_time("SRAM creation", datetime.datetime.now(), start_time)
@@ -58,9 +60,11 @@ class sram():
 
         # Save the spice file
         start_time = datetime.datetime.now()
-        spname = OPTS.output_path + sram.name + ".sp"
+        print(type(sram))
+        print(type(self))
+        spname = OPTS.output_path + self.s.name + ".sp"
         print("SP: Writing to {0}".format(spname))
-        sram.sp_write(spname)
+        self.s.sp_write(spname)
         print_time("Spice writing", datetime.datetime.now(), start_time)
 
         # Save the extracted spice file
@@ -68,7 +72,7 @@ class sram():
             start_time = datetime.datetime.now()
             # Output the extracted design if requested
             sp_file = OPTS.output_path + "temp_pex.sp"
-            verify.run_pex(sram.name, gdsname, spname, output=sp_file)
+            verify.run_pex(self.s.name, gdsname, spname, output=sp_file)
             print_time("Extraction", datetime.datetime.now(), start_time)
         else:
             # Use generated spice file for characterization
@@ -85,26 +89,26 @@ class sram():
                 print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
             if OPTS.trim_netlist:
                 print("Trimming netlist to speed up characterization.")
-        lib(out_dir=OPTS.output_path, sram=self, sp_file=sp_file)
+        lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
         print_time("Characterization", datetime.datetime.now(), start_time)
 
         # Write the layout
         start_time = datetime.datetime.now()
-        gdsname = OPTS.output_path + sram.name + ".gds"
+        gdsname = OPTS.output_path + self.s.name + ".gds"
         print("GDS: Writing to {0}".format(gdsname))
-        sram.gds_write(gdsname)
+        self.s.gds_write(gdsname)
         print_time("GDS", datetime.datetime.now(), start_time)
 
         # Create a LEF physical model
         start_time = datetime.datetime.now()
-        lefname = OPTS.output_path + sram.name + ".lef"
+        lefname = OPTS.output_path + self.s.name + ".lef"
         print("LEF: Writing to {0}".format(lefname))
-        sram.lef_write(lefname)
+        self.s.lef_write(lefname)
         print_time("LEF", datetime.datetime.now(), start_time)
 
         # Write a verilog model
         start_time = datetime.datetime.now()
-        vname = OPTS.output_path + sram.name + ".v"
+        vname = OPTS.output_path + self.s.name + ".v"
         print("Verilog: Writing to {0}".format(vname))
-        sram.verilog_write(vname)
+        self.s.verilog_write(vname)
         print_time("Verilog", datetime.datetime.now(), start_time)

compiler/sram_1bank.py

@@ -20,9 +20,6 @@ class sram_1bank(sram_base):
     def __init__(self, word_size, num_words, name):
         sram_base.__init__(self, word_size, num_words, 1, name)
 
-    def whoami(self):
-        print("1bank")
-        
     def add_modules(self):
         """ 
         This adds the moduels for a single bank SRAM with control
@@ -44,11 +41,16 @@ class sram_1bank(sram_base):
                           control_pos.y + self.control_logic.height + self.m1_pitch)
         self.add_addr_dff(addr_pos)
 
+        # Leave room for the control routes to the left of the flops
+        data_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch,
+                          control_pos.y + self.control_logic.height + self.m1_pitch)
+        self.add_addr_dff(addr_pos)
+        
         # two supply rails are already included in the bank, so just 2 here.
         self.width = self.bank.width + self.control_logic.width + 2*self.supply_rail_pitch
         self.height = self.bank.height 
 
-    def add_pins(self):
+    def add_layout_pins(self):
         """
         Add the top-level pins for a single bank SRAM with control.
         """
@@ -59,9 +61,14 @@ class sram_1bank(sram_base):
         for i in range(self.addr_size):
             self.copy_layout_pin(self.addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
 
+        for i in range(self.word_size):
+            self.copy_layout_pin(self.addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
+            
     def route(self):
         """ Route a single bank SRAM """
 
+        self.add_layout_pins()
+        
         # Route the outputs from the control logic module
         for n in self.control_logic_outputs:
             src_pin = self.control_logic_inst.get_pin(n)

compiler/sram_2bank.py

@@ -19,9 +19,6 @@ class sram_2bank(sram_base):
     def __init__(self, word_size, num_words, name):
         sram_base.__init__(self, word_size, num_words, 2, name)
 
-    def whoami(self):
-        print("2bank")
-        
     def compute_bank_offsets(self):
         """ Compute the overall offsets for a two bank SRAM """
 

compiler/sram_4bank.py

@@ -19,9 +19,6 @@ class sram_4bank(sram_base):
     def __init__(self, word_size, num_words, name):
         sram_base.__init__(self, word_size, num_words, 4, name)
 
-    def whoami(self):
-        print("4bank")
-        
     def compute_bank_offsets(self):
         """ Compute the overall offsets for a four bank SRAM """