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Reference local sram instance in sram.py.

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This commit is contained in:
Matt Guthaus
2018-07-13 09:30:14 -07:00
parent a4c29ea527
commit 0c23efe49b
4 changed files with 37 additions and 32 deletions
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compiler/sram.py
+25 -21
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@@ -25,28 +25,30 @@ class sram():
if num_banks == 1:
from sram_1bank import sram_1bank
sram=sram_1bank(word_size, num_words, name)
self.s=sram_1bank(word_size, num_words, name)
elif num_banks == 2:
from sram_2bank import sram_2bank
sram=sram_2bank(word_size, num_words, name)
self.s=sram_2bank(word_size, num_words, name)
elif num_banks == 4:
from sram_4bank import sram_4bank
sram=sram_4bank(word_size, num_words, name)
self.s=sram_4bank(word_size, num_words, name)
else:
debug.error("Invalid number of banks.",-1)
sram.compute_sizes()
sram.create_modules()
sram.add_pins()
sram.create_layout()
self.s.compute_sizes()
self.s.create_modules()
self.s.add_pins()
self.s.create_layout()
# Can remove the following, but it helps for debug!
sram.add_lvs_correspondence_points()
self.s.add_lvs_correspondence_points()
sram.offset_all_coordinates()
(sram.width, sram.height) = sram.find_highest_coords()
self.s.offset_all_coordinates()
highest_coord = self.s.find_highest_coords()
self.s.width = highest_coord[0]
self.s.height = highest_coord[1]
sram.DRC_LVS(final_verification=True)
self.s.DRC_LVS(final_verification=True)
if not OPTS.is_unit_test:
print_time("SRAM creation", datetime.datetime.now(), start_time)
@@ -58,9 +60,11 @@ class sram():
# Save the spice file
start_time = datetime.datetime.now()
spname = OPTS.output_path + sram.name + ".sp"
print(type(sram))
print(type(self))
spname = OPTS.output_path + self.s.name + ".sp"
print("SP: Writing to {0}".format(spname))
sram.sp_write(spname)
self.s.sp_write(spname)
print_time("Spice writing", datetime.datetime.now(), start_time)
# Save the extracted spice file
@@ -68,7 +72,7 @@ class sram():
start_time = datetime.datetime.now()
# Output the extracted design if requested
sp_file = OPTS.output_path + "temp_pex.sp"
verify.run_pex(sram.name, gdsname, spname, output=sp_file)
verify.run_pex(self.s.name, gdsname, spname, output=sp_file)
print_time("Extraction", datetime.datetime.now(), start_time)
else:
# Use generated spice file for characterization
@@ -85,26 +89,26 @@ class sram():
print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
if OPTS.trim_netlist:
print("Trimming netlist to speed up characterization.")
lib(out_dir=OPTS.output_path, sram=self, sp_file=sp_file)
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
print_time("Characterization", datetime.datetime.now(), start_time)
# Write the layout
start_time = datetime.datetime.now()
gdsname = OPTS.output_path + sram.name + ".gds"
gdsname = OPTS.output_path + self.s.name + ".gds"
print("GDS: Writing to {0}".format(gdsname))
sram.gds_write(gdsname)
self.s.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time)
# Create a LEF physical model
start_time = datetime.datetime.now()
lefname = OPTS.output_path + sram.name + ".lef"
lefname = OPTS.output_path + self.s.name + ".lef"
print("LEF: Writing to {0}".format(lefname))
sram.lef_write(lefname)
self.s.lef_write(lefname)
print_time("LEF", datetime.datetime.now(), start_time)
# Write a verilog model
start_time = datetime.datetime.now()
vname = OPTS.output_path + sram.name + ".v"
vname = OPTS.output_path + self.s.name + ".v"
print("Verilog: Writing to {0}".format(vname))
sram.verilog_write(vname)
self.s.verilog_write(vname)
print_time("Verilog", datetime.datetime.now(), start_time)