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Single banks working with new RBL

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This commit is contained in:
mrg
2019-07-11 14:47:27 -07:00
parent b841fd7ce3
commit 0b13225913
10 changed files with 176 additions and 107 deletions
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compiler/tests/18_port_data_test.py
+2 -2
View File
@@ -55,9 +55,9 @@ class port_data_test(openram_test):
self.local_check(a)
OPTS.bitcell = "bitcell_1w_1r"
OPTS.num_rw_ports = 1
OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
OPTS.num_w_ports = 1
c.num_words=16
c.words_per_row=1
compiler/tests/19_single_bank_1rw_1r_test.py
+4 -4
View File
@@ -32,7 +32,7 @@ class single_bank_1rw_1r_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create(module_type="bank", sram_config=c, num_ports=2)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=32
@@ -40,7 +40,7 @@ class single_bank_1rw_1r_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create(module_type="bank", sram_config=c, num_ports=2)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=64
@@ -48,7 +48,7 @@ class single_bank_1rw_1r_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c, num_ports=2)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.word_size=2
@@ -57,7 +57,7 @@ class single_bank_1rw_1r_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create(module_type="bank", sram_config=c, num_ports=2)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()
compiler/tests/19_single_bank_1w_1r_test.py
+4 -4
View File
@@ -32,7 +32,7 @@ class single_bank_1w_1r_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create(module_type="bank", sram_config=c, num_ports=2)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=32
@@ -40,7 +40,7 @@ class single_bank_1w_1r_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create(module_type="bank", sram_config=c, num_ports=2)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=64
@@ -48,7 +48,7 @@ class single_bank_1w_1r_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c, num_ports=2)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.word_size=2
@@ -57,7 +57,7 @@ class single_bank_1w_1r_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create(module_type="bank", sram_config=c, num_ports=2)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()
compiler/tests/19_single_bank_test.py
+4 -4
View File
@@ -28,7 +28,7 @@ class single_bank_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c, num_ports=1)
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=32
@@ -36,7 +36,7 @@ class single_bank_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c, num_ports=1)
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=64
@@ -44,7 +44,7 @@ class single_bank_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("bank", sram_config=c, num_ports=1)
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.word_size=2
@@ -53,7 +53,7 @@ class single_bank_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c, num_ports=1)
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()