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Remove extra rotated vias in bitcell array to simplify power routing

This commit is contained in:
Matt Guthaus 2018-11-29 18:13:15 -08:00
parent 0e7301fff8
commit 0af4263edb
3 changed files with 6 additions and 33 deletions
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35
compiler/modules/bitcell_array.py
View File

@ -132,40 +132,13 @@ class bitcell_array(design.design):
# increments to the next row height # increments to the next row height
offset.y += self.cell.height offset.y += self.cell.height
# For every second row and column, add a via for vdd # For every second row and column, add a via for gnd and vdd
for row in range(self.row_size): for row in range(self.row_size):
for col in range(self.column_size): for col in range(self.column_size):
inst = self.cell_inst[row,col] inst = self.cell_inst[row,col]
for vdd_pin in inst.get_pins("vdd"): for pin_name in ["vdd", "gnd"]:
# Drop to M1 if needed for pin in inst.get_pins(pin_name):
if vdd_pin.layer == "metal1": self.add_power_pin(pin_name, pin.center(), 90)
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=vdd_pin.center(),
rotate=90)
# Always drop to M2
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=vdd_pin.center())
self.add_layout_pin_rect_center(text="vdd",
layer="metal3",
offset=vdd_pin.center())
# For every second row and column (+1), add a via for gnd
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row,col]
for gnd_pin in inst.get_pins("gnd"):
# Drop to M1 if needed
if gnd_pin.layer == "metal1":
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=gnd_pin.center(),
rotate=90)
# Always drop to M2
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=gnd_pin.center())
self.add_layout_pin_rect_center(text="gnd",
layer="metal3",
offset=gnd_pin.center())
def analytical_delay(self, slew, load=0): def analytical_delay(self, slew, load=0):
from tech import drc from tech import drc

2
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
View File

@ -11,7 +11,7 @@ import globals
from globals import OPTS from globals import OPTS
import debug import debug
@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") #@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
class psram_1bank_2mux_1w_1r_test(openram_test): class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self): def runTest(self):

2
compiler/tests/20_psram_1bank_2mux_test.py
View File

@ -11,7 +11,7 @@ import globals
from globals import OPTS from globals import OPTS
import debug import debug
@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error") #@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error")
class psram_1bank_2mux_test(openram_test): class psram_1bank_2mux_test(openram_test):
def runTest(self): def runTest(self):