mirror of https://github.com/VLSIDA/OpenRAM.git
Add more layout and functional port tests.
This commit is contained in:
Matt Guthaus
parent
14fa33e21d
commit
0a16d83181
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@ -0,0 +1,50 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on a 1 bank SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
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class psram_1bank_2mux_1rw_1w_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from sram import sram
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from sram_config import sram_config
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 1
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OPTS.num_r_ports = 0
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.num_words=32
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c.words_per_row=2
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -12,7 +12,7 @@ from globals import OPTS
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import debug
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import debug
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#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
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#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
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class psram_1bank_2mux_test(openram_test):
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class psram_1bank_2mux_1w_1r_test(openram_test):
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def runTest(self):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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@ -30,7 +30,13 @@ class psram_1bank_2mux_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.num_words=32
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c.num_words=32
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c.words_per_row=2
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c.words_per_row=2
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debug.info(1, "Single bank two way column mux 1w/1r with control logic")
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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self.local_check(a, final_verification=True)
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@ -31,7 +31,13 @@ class psram_1bank_2mux_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.num_words=32
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c.num_words=32
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c.words_per_row=2
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c.words_per_row=2
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debug.info(1, "Single bank two way column mux with control logic")
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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self.local_check(a, final_verification=True)
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@ -0,0 +1,49 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on a 1 bank SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class psram_1bank_4mux_1rw_1r_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from sram import sram
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from sram_config import sram_config
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 1
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c = sram_config(word_size=4,
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num_words=64,
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num_banks=1)
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c.num_words=64
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c.words_per_row=4
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -29,7 +29,13 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=2
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c.words_per_row=2
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debug.info(1, "Single bank, two way column mux 1rw, 1r with control logic")
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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self.local_check(a, final_verification=True)
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@ -23,7 +23,13 @@ class sram_1bank_2mux_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=2
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c.words_per_row=2
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debug.info(1, "Single bank two way column mux with control logic")
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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self.local_check(a, final_verification=True)
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@ -23,7 +23,13 @@ class sram_1bank_4mux_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=4
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c.words_per_row=4
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debug.info(1, "Single bank, four way column mux with control logic")
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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self.local_check(a, final_verification=True)
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@ -0,0 +1,49 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on a 1 bank SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class sram_1bank_8mux_1rw_1r_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from sram import sram
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from sram_config import sram_config
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OPTS.bitcell = "bitcell_1rw_1r"
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OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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c = sram_config(word_size=2,
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num_words=128,
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num_banks=1)
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c.words_per_row=8
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -23,7 +23,13 @@ class sram_1bank_8mux_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=8
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c.words_per_row=8
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debug.info(1, "Single bank, eight way column mux with control logic")
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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self.local_check(a, final_verification=True)
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@ -29,7 +29,13 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=1
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c.words_per_row=1
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debug.info(1, "Single bank, no column mux 1rw, 1r with control logic")
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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self.local_check(a, final_verification=True)
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@ -23,7 +23,13 @@ class sram_1bank_nomux_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=1
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c.words_per_row=1
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debug.info(1, "Single bank, no column mux with control logic")
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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self.local_check(a, final_verification=True)
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@ -12,7 +12,7 @@ from globals import OPTS
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import debug
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import debug
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#@unittest.skip("SKIPPING 22_psram_1bank_2mux_func_test")
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#@unittest.skip("SKIPPING 22_psram_1bank_2mux_func_test")
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class psram_1bank_2mux_func_test(openram_test):
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class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
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def runTest(self):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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@ -35,10 +35,13 @@ class psram_1bank_2mux_func_test(openram_test):
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num_words=64,
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num_words=64,
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num_banks=1)
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num_banks=1)
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c.words_per_row=2
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c.words_per_row=2
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debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
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debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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c.num_words,
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OPTS.num_r_ports,
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c.words_per_row,
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OPTS.num_w_ports,
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c.num_banks))
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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s = sram(c, name="sram")
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s = sram(c, name="sram")
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tempspice = OPTS.openram_temp + "temp.sp"
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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s.sp_write(tempspice)
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@ -35,10 +35,13 @@ class psram_1bank_nomux_func_test(openram_test):
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num_words=32,
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num_words=32,
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num_banks=1)
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num_banks=1)
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c.words_per_row=1
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c.words_per_row=1
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debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
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debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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c.num_words,
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OPTS.num_r_ports,
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c.words_per_row,
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OPTS.num_w_ports,
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c.num_banks))
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c.word_size,
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c.num_words,
|
||||||
|
c.words_per_row,
|
||||||
|
c.num_banks))
|
||||||
s = sram(c, name="sram")
|
s = sram(c, name="sram")
|
||||||
tempspice = OPTS.openram_temp + "temp.sp"
|
tempspice = OPTS.openram_temp + "temp.sp"
|
||||||
s.sp_write(tempspice)
|
s.sp_write(tempspice)
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue