Improve output format. Rename option to be more sensible.

This commit is contained in:
mguthaus
2017-11-22 15:57:29 -08:00
parent cf66c83fe4
commit 09ca8ba17d
15 changed files with 58 additions and 36 deletions
+1 -1
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@@ -21,7 +21,7 @@ class timing_sram_test(unittest.TestCase):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version="hspice"
OPTS.spice_name="hspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
+1 -1
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@@ -22,7 +22,7 @@ class timing_setup_test(unittest.TestCase):
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version="hspice"
OPTS.spice_name="hspice"
OPTS.analytical_delay = False
import characterizer
reload(characterizer)
+2 -2
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@@ -19,7 +19,7 @@ class timing_sram_test(unittest.TestCase):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version="ngspice"
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
@@ -82,7 +82,7 @@ class timing_sram_test(unittest.TestCase):
# reset these options
OPTS.check_lvsdrc = True
OPTS.spice_version="hspice"
OPTS.spice_name="hspice"
OPTS.analytical_delay = True
reload(characterizer)
+2 -2
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@@ -22,7 +22,7 @@ class timing_setup_test(unittest.TestCase):
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version="ngspice"
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
@@ -61,7 +61,7 @@ class timing_setup_test(unittest.TestCase):
# reset these options
OPTS.check_lvsdrc = True
OPTS.spice_version="hspice"
OPTS.spice_name="hspice"
OPTS.analytical_delay = True
reload(characterizer)
+2 -2
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@@ -64,7 +64,7 @@ class sram_func_test(unittest.TestCase):
import os
if OPTS.spice_version == "hspice":
if OPTS.spice_name == "hspice":
cmd = "hspice -mt 2 -i {0} > {1} ".format(
simulator_file, result_file)
else:
@@ -145,7 +145,7 @@ class sram_func_test(unittest.TestCase):
9.5 * tech.spice["clock_period"], 10 * tech.spice["clock_period"]))
sim_file.write("\n")
if OPTS.spice_version == "hspice":
if OPTS.spice_name in ["hspice","xa"]:
sim_file.write(".probe v(x*.*)\n")
sim_file.write(".tran 0.1ns {0}ns\n".format(
10 * tech.spice["clock_period"]))
+1 -1
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@@ -22,7 +22,7 @@ class sram_func_test(unittest.TestCase):
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version="hspice"
OPTS.spice_name="hspice"
OPTS.analytical_delay = False
import characterizer
reload(characterizer)
+1 -1
View File
@@ -18,7 +18,7 @@ class lib_test(unittest.TestCase):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version="hspice"
OPTS.spice_name="hspice"
OPTS.analytical_delay = False
import characterizer
reload(characterizer)