mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-07 11:21:14 +02:00
Improve output format. Rename option to be more sensible.
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@@ -21,7 +21,7 @@ class timing_sram_test(unittest.TestCase):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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OPTS.spice_version="hspice"
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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import characterizer
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@@ -22,7 +22,7 @@ class timing_setup_test(unittest.TestCase):
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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OPTS.spice_version="hspice"
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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import characterizer
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reload(characterizer)
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@@ -19,7 +19,7 @@ class timing_sram_test(unittest.TestCase):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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OPTS.spice_version="ngspice"
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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import characterizer
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@@ -82,7 +82,7 @@ class timing_sram_test(unittest.TestCase):
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# reset these options
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OPTS.check_lvsdrc = True
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OPTS.spice_version="hspice"
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = True
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reload(characterizer)
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@@ -22,7 +22,7 @@ class timing_setup_test(unittest.TestCase):
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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OPTS.spice_version="ngspice"
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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import characterizer
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@@ -61,7 +61,7 @@ class timing_setup_test(unittest.TestCase):
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# reset these options
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OPTS.check_lvsdrc = True
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OPTS.spice_version="hspice"
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = True
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reload(characterizer)
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@@ -64,7 +64,7 @@ class sram_func_test(unittest.TestCase):
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import os
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if OPTS.spice_version == "hspice":
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if OPTS.spice_name == "hspice":
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cmd = "hspice -mt 2 -i {0} > {1} ".format(
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simulator_file, result_file)
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else:
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@@ -145,7 +145,7 @@ class sram_func_test(unittest.TestCase):
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9.5 * tech.spice["clock_period"], 10 * tech.spice["clock_period"]))
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sim_file.write("\n")
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if OPTS.spice_version == "hspice":
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if OPTS.spice_name in ["hspice","xa"]:
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sim_file.write(".probe v(x*.*)\n")
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sim_file.write(".tran 0.1ns {0}ns\n".format(
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10 * tech.spice["clock_period"]))
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@@ -22,7 +22,7 @@ class sram_func_test(unittest.TestCase):
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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OPTS.spice_version="hspice"
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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import characterizer
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reload(characterizer)
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@@ -18,7 +18,7 @@ class lib_test(unittest.TestCase):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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OPTS.spice_version="hspice"
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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import characterizer
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reload(characterizer)
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