mirror of https://github.com/VLSIDA/OpenRAM.git
cast pins dict to list
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5907cbb3e2
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@ -42,7 +42,7 @@ class column_decoder(design):
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def create_instances(self):
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self.column_decoder_inst = self.add_inst(name="column_decoder",
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mod=self.column_decoder)
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self.connect_inst(self.pins)
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self.connect_inst(list(self.pins))
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def create_layout(self):
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self.column_decoder_inst.place(vector(0,0))
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@ -1212,7 +1212,7 @@ class pbitcell(bitcell_base):
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if self.dummy_bitcell:
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return
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pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
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pin_dict = {pin: port for pin, port in zip(list(self.pins), port_nets)}
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# Edges added wl->bl, wl->br for every port except write ports
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rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)
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