mirror of https://github.com/VLSIDA/OpenRAM.git
cast pins dict to list
This commit is contained in:
parent
5907cbb3e2
commit
09aa395174
|
|
@ -42,7 +42,7 @@ class column_decoder(design):
|
||||||
def create_instances(self):
|
def create_instances(self):
|
||||||
self.column_decoder_inst = self.add_inst(name="column_decoder",
|
self.column_decoder_inst = self.add_inst(name="column_decoder",
|
||||||
mod=self.column_decoder)
|
mod=self.column_decoder)
|
||||||
self.connect_inst(self.pins)
|
self.connect_inst(list(self.pins))
|
||||||
|
|
||||||
def create_layout(self):
|
def create_layout(self):
|
||||||
self.column_decoder_inst.place(vector(0,0))
|
self.column_decoder_inst.place(vector(0,0))
|
||||||
|
|
|
||||||
|
|
@ -1212,7 +1212,7 @@ class pbitcell(bitcell_base):
|
||||||
if self.dummy_bitcell:
|
if self.dummy_bitcell:
|
||||||
return
|
return
|
||||||
|
|
||||||
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
|
pin_dict = {pin: port for pin, port in zip(list(self.pins), port_nets)}
|
||||||
|
|
||||||
# Edges added wl->bl, wl->br for every port except write ports
|
# Edges added wl->bl, wl->br for every port except write ports
|
||||||
rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)
|
rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue