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Added bitcell check to storage nodes.
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@@ -45,7 +45,9 @@ class timing_sram_test(openram_test):
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c.recompute_sizes()
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debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
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s = factory.create(module_type="sram", sram_config=c)
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#import sys
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#sys.exit(1)
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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