Added bitcell check to storage nodes.

compiler/modules/bank.py

@@ -1286,4 +1286,8 @@ class bank(design.design):
         """Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
         for inst in self.precharge_array_inst:
             if inst != None:
-                self.graph_inst_exclude.add(inst)
+                self.graph_inst_exclude.add(inst)
+                
+    def get_cell_name(self, inst_name, row, col):
+        """Gets the spice name of the target bitcell."""
+        return self.bitcell_array_inst.mod.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col)            

compiler/modules/bitcell_array.py

@@ -210,4 +210,6 @@ class bitcell_array(design.design):
                     continue
                 self.graph_inst_exclude.add(self.cell_inst[row,col])
             
-            
+    def get_cell_name(self, inst_name, row, col):
+        """Gets the spice name of the target bitcell.""" 
+        return inst_name+'.x'+self.cell_inst[row,col].name, self.cell_inst[row,col]