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Bugra Onal 2022-01-26 07:47:37 -08:00
parent 859548f19f
commit 0970095415
1 changed files with 49 additions and 20 deletions
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69
compiler/sram/multibank_template.v
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@ -1,36 +1,65 @@
module multibank # ( module multibank # (
DATA_WIDTH = 32, DATA_WIDTH = 32,
ADDR_WIDTH= 8 ADDR_WIDTH= 8,
NUM_BANKS=2
)( )(
#<RW_PORTS #<RW_PORTS
clk#$PORT_NUM$#, clk,
addr#$PORT_NUM$#, addr,
din#$PORT_NUM$#, din,
csb#$PORT_NUM$#, csb,
web#$PORT_NUM$#, web,
dout#$PORT_NUM$#, dout,
#>RW_PORTS #>RW_PORTS
#<R_PORTS #<R_PORTS
clk#$PORT_NUM$#, clk,
addr#$PORT_NUM$#, addr,
csb#$PORT_NUM$#, csb,
web#$PORT_NUM$#, web,
dout#$PORT_NUM$#, dout,
#>R_PORTS #>R_PORTS
); );
parameter RAM_DEPTH = 1 << ADRR_WIDTH; parameter RAM_DEPTH = 1 << ADRR_WIDTH;
parameter BANK_SEL = (NUM_BANKS <= 2)? 1 :
(NUM_BANKS <= 4)? 2 :
(NUM_BANKS <= 8)? 3 :
(NUM_BANKS <= 16)? 4 : 5;
input clk;
input [ADDR_WIDTH -1 : 0] addr;
input [DATA_WIDTH - 1: 0] din;
input csb;
input web;
output reg [DATA_WIDTH - 1 : 0] data;
#<BANK_DEFS
reg csb#$PORT_NUM$#;
reg web#$PORT_NUM$#;
reg dout#$PORT_NUM$#;
#>BANK_DEFS
#<BANK_INIT #<BANK_INIT
bank bank#$BANK_NUM$# #(DATA_WIDTH, ADDR_WIDTH) ( bank bank#$BANK_NUM$# #(DATA_WIDTH, ADDR_WIDTH) (
#<BANK_RW_PORTS #<BANK_RW_PORTS
clk#$PORT_NUM$#, .clk(clk),
addr#$PORT_NUM$#, .addr(addr),
din#$PORT_NUM$#, .din(din),
csb#$PORT_NUM$#, .csb(csb#$PORT_NUM$#),
web#$PORT_NUM$#, .web(web#$PORT_NUM$#),
dout#$PORT_NUM$#, .dout(dout#$PORT_NUM$#),
#>BANK_R_PORTS #>BANK_RW_PORTS
) )
#>BANK_INIT #>BANK_INIT
always @(posedge clk) begin
case (addr[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
#<BANK_CASE
#$PORT_NUM$#: begin
dout <= dout#$PORT_NUM$#;
web#$PORT_NUM$# <= web;
end
#>BANK_CASE
endcase
end