luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix base bitcell syntax error. Remove some unused imports.

This commit is contained in:
mrg 2020-01-30 01:58:30 +00:00
parent 79391b84da
commit 0880c393fd
2 changed files with 3 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
compiler/modules/dummy_array.py
View File

@ -3,15 +3,11 @@
# Copyright (c) 2016-2019 Regents of the University of California
# All rights reserved.
#
import debug
import design
from base_array import bitcell_base_array
from tech import drc
import contact
from bitcell_base_array import bitcell_base_array
from sram_factory import factory
from vector import vector
from globals import OPTS
class dummy_array(bitcell_base_array):
"""
Generate a dummy row/column for the replica array.
@ -24,7 +20,6 @@ class dummy_array(bitcell_base_array):
if not OPTS.netlist_only:
self.create_layout()
def create_netlist(self):
""" Create and connect the netlist """
self.add_modules()

5
compiler/modules/replica_bitcell_array.py
View File

@ -10,10 +10,7 @@ from tech import drc, spice
from vector import vector
from globals import OPTS
from sram_factory import factory
import logical_effort
import bitcell_array
import replica_column
import dummy_array
class replica_bitcell_array(design.design):
"""