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Only copy end-cap pins to the bank level

This commit is contained in:
mrg 2020-06-29 11:46:59 -07:00
parent 1bc0775810
commit 07d0f3af8e
2 changed files with 11 additions and 6 deletions
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4
compiler/base/hierarchy_layout.py
View File

@ -1101,7 +1101,7 @@ class layout():
height=ymax - ymin) height=ymax - ymin)
return rect return rect
def copy_power_pins(self, inst, name): def copy_power_pins(self, inst, name, add_vias=True):
""" """
This will copy a power pin if it is on the lowest power_grid layer. This will copy a power pin if it is on the lowest power_grid layer.
If it is on M1, it will add a power via too. If it is on M1, it will add a power via too.
@ -1115,7 +1115,7 @@ class layout():
pin.width(), pin.width(),
pin.height()) pin.height())
else: elif add_vias:
self.add_power_pin(name, pin.center(), start_layer=pin.layer) self.add_power_pin(name, pin.center(), start_layer=pin.layer)
def add_power_pin(self, name, loc, size=[1, 1], directions=None, start_layer="m1"): def add_power_pin(self, name, loc, size=[1, 1], directions=None, start_layer="m1"):

13
compiler/modules/bank.py
View File

@ -132,14 +132,17 @@ class bank(design.design):
# Connect the rbl to the port data pin # Connect the rbl to the port data pin
bl_pin = self.port_data_inst[port].get_pin("rbl_bl") bl_pin = self.port_data_inst[port].get_pin("rbl_bl")
if port % 2: if port % 2:
pin_offset = bl_pin.uc() pin_pos = bl_pin.uc()
pin_offset = pin_pos + vector(0, self.m3_pitch)
left_right_offset = vector(self.max_x_offset, pin_offset.y) left_right_offset = vector(self.max_x_offset, pin_offset.y)
else: else:
pin_offset = bl_pin.bc() pin_pos = bl_pin.bc()
pin_offset = pin_pos - vector(0, self.m3_pitch)
left_right_offset = vector(self.min_x_offset, pin_offset.y) left_right_offset = vector(self.min_x_offset, pin_offset.y)
self.add_via_stack_center(from_layer=bl_pin.layer, self.add_via_stack_center(from_layer=bl_pin.layer,
to_layer="m3", to_layer="m3",
offset=pin_offset) offset=pin_offset)
self.add_path(bl_pin.layer, [pin_offset, pin_pos])
self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port), self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port),
layer="m3", layer="m3",
start=left_right_offset, start=left_right_offset,
@ -583,9 +586,11 @@ class bank(design.design):
def route_supplies(self): def route_supplies(self):
""" Propagate all vdd/gnd pins up to this level for all modules """ """ Propagate all vdd/gnd pins up to this level for all modules """
# Copy only the power pins already on the power layer
# (this won't add vias to internal bitcell pins, for example)
for inst in self.insts: for inst in self.insts:
self.copy_power_pins(inst, "vdd") self.copy_power_pins(inst, "vdd", add_vias=False)
self.copy_power_pins(inst, "gnd") self.copy_power_pins(inst, "gnd", add_vias=False)
def route_bank_select(self, port): def route_bank_select(self, port):
""" Route the bank select logic. """ """ Route the bank select logic. """