label bitcell in stim, add s_en top level to stim

compiler/characterizer/delay.py

@@ -221,8 +221,9 @@ class delay(simulation):
             q_name = cell_name+'.'+str(storage_names[0])
             qbar_name = cell_name+'.'+str(storage_names[1])
         else:
-            q_name = "bitcell_Q_r{0}_c{1}".format(OPTS.num_words -1, OPTS.word_size-1)
+            bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col)
-            qbar_name = "bitcell_Q_r{0}_c{1}".format(OPTS.num_words -1, OPTS.word_size-1)
+            q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col)
+            qbar_name = "bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col)
         
         # Bit measures, measurements times to be defined later. The measurement names must be unique
         # but they is enforced externally
@@ -284,6 +285,8 @@ class delay(simulation):
         debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.")
         enable_name = sa_mods[0].get_enable_name()
         sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0])
+        if OPTS.use_pex:
+            #get sense amp multi bank
         return sen_name        
      
     def get_bl_name(self, paths, port):

compiler/characterizer/stimuli.py

@@ -52,10 +52,12 @@ class stimuli():
         for pin in pins:
             self.sf.write("{0} ".format(pin))
         if OPTS.use_pex:
-            for row in range(0,OPTS.num_words):
+            for bank in range(OPTS.num_banks):
-                for col in range(0,OPTS.word_size):
+                for row in range(OPTS.num_words):
-                    self.sf.write("bitcell_Q_r{0}_c{1} ".format(row,col))
+                    for col in range(OPTS.word_size):
-                    self.sf.write("bitcell_Q_bar_r{0}_c{1} ".format(row,col))
+                        self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
+                        self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
+                self.sf.write("s_en{0} ".format(bank))
         self.sf.write("{0}\n".format(model_name))
 
 

compiler/sram/sram_1bank.py

@@ -489,3 +489,6 @@ class sram_1bank(sram_base):
         if inst_name.find('x') != 0:
             inst_name = 'x'+inst_name
         return self.bank_inst.mod.get_cell_name(inst_name+'.x'+self.bank_inst.name, row, col)
+    
+    def get_bank_num(self, inst_name, row, col):
+        return 0;

compiler/verify/magic.py

@@ -309,7 +309,7 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
     out_errors = find_error(results)
     debug.check(os.path.isfile(output),"Couldn't find PEX extracted output.")
 
-    #correct_port(name,output,sp_name)
+    correct_port(name,output,sp_name)
     return out_errors
 
 def write_batch_pex_rule(gds_name,name,sp_name,output):
@@ -375,7 +375,7 @@ def write_script_pex_rule(gds_name,cell_name,output):
     else:
         pre = ""
     f.write(pre+"extract\n".format(cell_name))
-    f.write(pre+"ext2spice hierarchy on\n")
+    f.write(pre+"ext2spice hierarchy off\n")
     f.write(pre+"ext2spice format ngspice\n")
     f.write(pre+"ext2spice renumber off\n")
     f.write(pre+"ext2spice scale off\n")
@@ -414,14 +414,20 @@ def correct_port(name, output_file_name, ref_file_name):
     part2 = pex_file.read()
 
     bitcell_list = "+ "
-    for row in range(0,OPTS.num_words):
+    for bank in range(OPTS.num_banks):
-        for col in range(0,OPTS.word_size):
+        for row in range(OPTS.num_words):
-            bitcell_list += "bitcell_Q_r{0}_c{1} ".format(row,col)
+            for col in range(OPTS.word_size):
-            bitcell_list += "bitcell_Q_bar_r{0}_c{1} ".format(row,col)
+                bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col)
+                bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col)
     bitcell_list += "\n"
 
+    control_list = "+ "
+    for bank in range(OPTS.num_banks):
+        control_list += "s_en{0}".format(bank)
+    control_list += '\n'
+
+    part2 = bitcell_list + control_list + part2
 
-    part2 = bitcell_list + part2
     pex_file.close()
 
     # obtain the correct definition line from the original spice file