mirror of https://github.com/VLSIDA/OpenRAM.git
Fix pinvbuf layers
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parent
14782914b3
commit
064fe34edf
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@ -9,7 +9,7 @@ import debug
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import pgate
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import pgate
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from vector import vector
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from vector import vector
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from sram_factory import factory
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from sram_factory import factory
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from tech import layer
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class pinvbuf(pgate.pgate):
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class pinvbuf(pgate.pgate):
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"""
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"""
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@ -111,33 +111,45 @@ class pinvbuf(pgate.pgate):
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mirror="MX")
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mirror="MX")
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def route_wires(self):
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def route_wires(self):
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if "li" in layer:
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route_stack = self.li_stack
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else:
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route_stack = self.m1_stack
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# inv1 Z to inv2 A
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# inv1 Z to inv2 A
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z1_pin = self.inv1_inst.get_pin("Z")
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z1_pin = self.inv1_inst.get_pin("Z")
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a2_pin = self.inv2_inst.get_pin("A")
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a2_pin = self.inv2_inst.get_pin("A")
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mid_point = vector(z1_pin.cx(), a2_pin.cy())
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mid_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_path("m1", [z1_pin.center(), mid_point, a2_pin.center()])
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self.add_path(z1_pin.layer, [z1_pin.center(), mid_point, a2_pin.center()])
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self.add_via_stack_center(from_layer=z1_pin.layer,
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to_layer=a2_pin.layer,
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offset=a2_pin.center())
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# inv2 Z to inv3 A
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# inv2 Z to inv3 A
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z2_pin = self.inv2_inst.get_pin("Z")
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z2_pin = self.inv2_inst.get_pin("Z")
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a3_pin = self.inv3_inst.get_pin("A")
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a3_pin = self.inv3_inst.get_pin("A")
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mid_point = vector(z2_pin.cx(), a3_pin.cy())
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mid_point = vector(z2_pin.cx(), a3_pin.cy())
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self.add_path("m1", [z2_pin.center(), mid_point, a3_pin.center()])
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self.add_path(z2_pin.layer, [z2_pin.center(), mid_point, a3_pin.center()])
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self.add_via_stack_center(from_layer=z2_pin.layer,
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to_layer=a3_pin.layer,
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offset=a3_pin.center())
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# inv1 Z to inv4 A (up and over)
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# inv1 Z to inv4 A (up and over)
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z1_pin = self.inv1_inst.get_pin("Z")
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z1_pin = self.inv1_inst.get_pin("Z")
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a4_pin = self.inv4_inst.get_pin("A")
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a4_pin = self.inv4_inst.get_pin("A")
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mid_point = vector(z1_pin.cx(), a4_pin.cy())
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mid_point = vector(z1_pin.cx(), a4_pin.cy())
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self.add_wire(self.m1_stack,
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self.add_wire(route_stack,
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[z1_pin.center(), mid_point, a4_pin.center()])
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[z1_pin.center(), mid_point, a4_pin.center()])
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self.add_via_center(layers=self.m1_stack,
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self.add_via_stack_center(from_layer=z1_pin.layer,
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offset=z1_pin.center())
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to_layer=route_stack[2],
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offset=z1_pin.center())
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def add_layout_pins(self):
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def add_layout_pins(self):
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# Continous vdd rail along with label.
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# Continous vdd rail along with label.
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vdd_pin = self.inv1_inst.get_pin("vdd")
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vdd_pin = self.inv1_inst.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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self.add_layout_pin(text="vdd",
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layer="m1",
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layer=vdd_pin.layer,
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offset=vdd_pin.ll().scale(0, 1),
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offset=vdd_pin.ll().scale(0, 1),
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width=self.width,
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width=self.width,
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height=vdd_pin.height())
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height=vdd_pin.height())
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@ -145,7 +157,7 @@ class pinvbuf(pgate.pgate):
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# Continous vdd rail along with label.
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# Continous vdd rail along with label.
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gnd_pin = self.inv4_inst.get_pin("gnd")
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gnd_pin = self.inv4_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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self.add_layout_pin(text="gnd",
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layer="m1",
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layer=gnd_pin.layer,
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offset=gnd_pin.ll().scale(0, 1),
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offset=gnd_pin.ll().scale(0, 1),
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width=self.width,
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width=self.width,
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height=gnd_pin.height())
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height=gnd_pin.height())
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@ -153,31 +165,25 @@ class pinvbuf(pgate.pgate):
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# Continous gnd rail along with label.
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# Continous gnd rail along with label.
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gnd_pin = self.inv1_inst.get_pin("gnd")
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gnd_pin = self.inv1_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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self.add_layout_pin(text="gnd",
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layer="m1",
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layer=gnd_pin.layer,
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offset=gnd_pin.ll().scale(0, 1),
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offset=gnd_pin.ll().scale(0, 1),
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width=self.width,
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width=self.width,
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height=vdd_pin.height())
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height=vdd_pin.height())
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z_pin = self.inv4_inst.get_pin("Z")
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z_pin = self.inv4_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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self.add_layout_pin_rect_center(text="Z",
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layer="m2",
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layer=z_pin.layer,
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offset=z_pin.center())
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offset=z_pin.center())
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self.add_via_center(layers=self.m1_stack,
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offset=z_pin.center())
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zb_pin = self.inv3_inst.get_pin("Z")
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zb_pin = self.inv3_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Zb",
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self.add_layout_pin_rect_center(text="Zb",
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layer="m2",
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layer=zb_pin.layer,
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offset=zb_pin.center())
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offset=zb_pin.center())
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self.add_via_center(layers=self.m1_stack,
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offset=zb_pin.center())
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a_pin = self.inv1_inst.get_pin("A")
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a_pin = self.inv1_inst.get_pin("A")
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self.add_layout_pin_rect_center(text="A",
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self.add_layout_pin_rect_center(text="A",
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layer="m2",
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layer=a_pin.layer,
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offset=a_pin.center())
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offset=a_pin.center())
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self.add_via_center(layers=self.m1_stack,
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offset=a_pin.center())
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def determine_clk_buf_stage_efforts(self, external_cout, inp_is_rise=False):
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def determine_clk_buf_stage_efforts(self, external_cout, inp_is_rise=False):
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"""Get the stage efforts of the clk -> clk_buf path"""
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"""Get the stage efforts of the clk -> clk_buf path"""
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