mirror of https://github.com/VLSIDA/OpenRAM.git
Initial files for gf180
This commit is contained in:
mrg
SWalker
parent
decfd7ff4f
commit
06058e1b87
17
Makefile
17
Makefile
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@ -21,12 +21,18 @@ OPEN_PDKS_GIT_REPO ?= https://github.com/RTimothyEdwards/open_pdks.git
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OPEN_PDKS_GIT_COMMIT ?= 1.0.311
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#OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608
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SKY130_PDK ?= $(PDK_ROOT)/sky130A
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GF180_PDK ?= $(PDK_ROOT)/gf180
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# Skywater PDK
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SKY130_PDKS_DIR ?= $(PDK_ROOT)/skywater-pdk
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SKY130_PDKS_GIT_REPO ?= https://github.com/google/skywater-pdk.git
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SKY130_PDKS_GIT_COMMIT ?= f70d8ca46961ff92719d8870a18a076370b85f6c
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# GF180 PDK
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GF180_PDKS_DIR ?= $(PDK_ROOT)/gf180mcu-pdk
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GF180_PDKS_GIT_REPO ?= https://github.com/google/gf180mcu-pdk.git
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GF180_PDKS_GIT_COMMIT ?= main
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# Create lists of all the files to copy/link
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GDS_FILES := $(sort $(wildcard $(SRAM_LIB_DIR)/cells/*/*.gds))
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GDS_FILES := $(GDS_FILES) $(PDK_ROOT)/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_1.gds
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@ -67,7 +73,16 @@ $(SKY130_PDKS_DIR): check-pdk-root
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@git -C $(SKY130_PDKS_DIR) checkout $(SKY130_PDKS_GIT_COMMIT) && \
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git -C $(SKY130_PDKS_DIR) submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest
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$(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR)
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$(GF180_PDKS_DIR): check-pdk-root
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@echo "Cloning gf PDK..."
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@[ -d $(PDK_ROOT)/gf180mcu-pdk ] || \
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git clone https://github.com/google/gf180mcu-pdk.git $(PDK_ROOT)/gf180mcu-pdk
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@cd $(SKY130_PDKS_DIR) && \
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git checkout main && git pull && \
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git checkout -qf $(GF180_PDKS_GIT_COMMIT) && \
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git submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest
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$(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR) $(GF180_PDKS_DIR)
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@echo "Cloning open_pdks..."
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@[ -d $(OPEN_PDKS_DIR) ] || \
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git clone $(OPEN_PDKS_GIT_REPO) $(OPEN_PDKS_DIR)
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@ -6,4 +6,5 @@
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export OPENRAM_HOME="`pwd`/compiler"
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export OPENRAM_TECH="`pwd`/technology"
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export PDK_ROOT="$HOME/gf/pdk"
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export PYTHONPATH=$OPENRAM_HOME
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@ -0,0 +1,52 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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#!/usr/bin/python
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"""
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This type of setup script should be placed in the setup_scripts directory in the trunk
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"""
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import sys
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import os
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TECHNOLOGY = "gf180"
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os.environ["MGC_TMPDIR"] = "/tmp"
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###########################
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# OpenRAM Paths
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# OpenPDK needed for magicrc, tech file and spice models of transistors
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if 'PDK_ROOT' in os.environ:
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open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180', 'libs.tech')
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else:
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raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.")
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# The ngspice models work with Xyce too now
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spice_model_dir = os.path.join(open_pdks, "ngspice")
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gf180_lib_ngspice = os.path.join(open_pdks, "ngspice", "gf180.lib.spice")
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if not os.path.exists(gf180_lib_ngspice):
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raise SystemError("Did not find {} under {}".format(gf180_lib_ngspice, open_pdks))
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os.environ["SPICE_MODEL_DIR"] = spice_model_dir
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open_pdks = os.path.abspath(open_pdks)
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gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180A.magicrc")
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if not os.path.exists(gf180_magicrc):
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raise SystemError("Did not find {} under {}".format(gf180_magicrc, open_pdks))
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os.environ["OPENRAM_MAGICRC"] = gf180_magicrc
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gf180_netgenrc = os.path.join(open_pdks, 'netgen', "setup.tcl")
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if not os.path.exists(gf180_netgenrc):
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raise SystemError("Did not find {} under {}".format(gf180_netgenrc, open_pdks))
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os.environ["OPENRAM_NETGENRC"] = gf180_netgenrc
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try:
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DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME"))
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except:
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DRCLVS_HOME= "not-found"
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os.environ["DRCLVS_HOME"] = DRCLVS_HOME
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@ -0,0 +1,454 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import os
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import drc as d
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#from drc.design_rules import design_rules
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#from drc.module_type import module_type
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#from drc.custom_cell_properties import cell_properties
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#from drc.custom_layer_properties import layer_properties
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"""
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File containing the process technology parameters for SCMOS 4m, 0.35um
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"""
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###################################################
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# Custom modules
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###################################################
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# This uses the default classes to instantiate module from
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# '$OPENRAM_HOME/compiler/modules'.
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# Using tech_modules['cellname'] you can override each class by providing a custom
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# implementation in '$OPENRAM_TECHDIR/modules/'
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# For example: tech_modules['contact'] = 'contact_scn4m'
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tech_modules = d.module_type()
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###################################################
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# Custom cell properties
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###################################################
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cell_properties = d.cell_properties()
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###################################################
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# Custom cell properties
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###################################################
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layer_properties = d.layer_properties()
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###################################################
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# GDS file info
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###################################################
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GDS={}
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# gds units
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# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
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#is the size of a database unit in user units. The second is the size
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#of a database unit in meters. For example, if your library was
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#created with the default units (user unit = 1 m and 1000 database
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#units per user unit), then the first number would be 0.001 and the
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#second number would be 10-9. Typically, the first number is less than
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#1, since you use more than 1 database unit per user unit. To
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#calculate the size of a user unit in meters, divide the second number
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#by the first."
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GDS["unit"]=(0.001,1e-6)
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# default label zoom
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GDS["zoom"] = 0.5
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###################################################
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# Interconnect stacks
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###################################################
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poly_stack = ("poly", "contact", "m1")
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active_stack = ("active", "contact", "m1")
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m1_stack = ("m1", "via1", "m2")
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m2_stack = ("m2", "via2", "m3")
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m3_stack = ("m3", "via3", "m4")
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layer_indices = {"poly": 0,
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"active": 0,
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"m1": 1,
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"m2": 2,
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"m3": 3,
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"m4": 4}
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# The FEOL stacks get us up to m1
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feol_stacks = [poly_stack,
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active_stack]
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# The BEOL stacks are m1 and up
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beol_stacks = [m1_stack,
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m2_stack,
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m3_stack]
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layer_stacks = feol_stacks + beol_stacks
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preferred_directions = {"poly": "V",
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"active": "V",
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"m1": "H",
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"m2": "V",
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"m3": "H",
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"m4": "V"}
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###################################################
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# Power grid
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###################################################
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# Use M3/M4
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power_grid = m3_stack
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###################################################
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##GDS Layer Map
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###################################################
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# create the GDS layer map
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layer={}
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layer["pwell"] = (204, 0)
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layer["nwell"] = (21, 0)
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layer["dnwell"] = (12, 0)
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layer["active"] = (22, 0)
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layer["pimplant"] = (31, 0)
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layer["nimplant"] = (32, 0)
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layer["poly"] = (30, 0)
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layer["contact"] = (33, 0)
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layer["m1"] = (34, 0)
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layer["via1"] = (35, 0)
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layer["m2"] = (36, 0)
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layer["via2"] = (38, 0)
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layer["m3"] = (42, 0)
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layer["via3"] = (40, 0)
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layer["m4"] = (46, 0)
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layer["via4"] = (41, 0)
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layer["m5"] = (81, 0)
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# Not an official layer
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layer["text"] = (234, 5)
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layer["mem"] = (108, 5)
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layer["boundary"] = (0, 0)
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label_purpose = 10
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#use_purpose = {}
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# Layer names for external PDKs
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layer_names = {}
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layer_names["active"] = "active"
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layer_names["pwell"] = "pwell"
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layer_names["nwell"] = "nwell"
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layer_names["nimplant"]= "nimplant"
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layer_names["pimplant"]= "pimplant"
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layer_names["poly"] = "poly"
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layer_names["contact"] = "contact"
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layer_names["m1"] = "metal1"
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layer_names["via1"] = "via1"
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layer_names["m2"] = "metal2"
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layer_names["via2"] = "via2"
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layer_names["m3"] = "metal3"
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layer_names["via3"] = "via3"
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layer_names["m4"] = "metal4"
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layer_names["text"] = "text"
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layer_names["mem"] = "SramCore"
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layer_names["boundary"]= "boundary"
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###################################################
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# DRC/LVS Rules Setup
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###################################################
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# technology parameter
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parameter={}
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# difftap.2b
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parameter["min_tx_size"] = 0.250
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parameter["beta"] = 3
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parameter["6T_inv_nmos_size"] = 0.205
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parameter["6T_inv_pmos_size"] = 0.09
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parameter["6T_access_size"] = 0.135
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drc = d.design_rules("gf180")
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# grid size
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drc["grid"] = 0.005
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# minwidth_tx with contact (no dog bone transistors)
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# difftap.2b
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drc["minwidth_tx"] = 0.360
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drc["minlength_channel"] = 0.150
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drc["pwell_to_nwell"] = 0
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# nwell.1 Minimum width of nwell/pwell
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drc.add_layer("nwell",
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width=0.840,
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spacing=1.270)
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# poly.1a Minimum width of poly
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# poly.2 Minimum spacing of poly AND active
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drc.add_layer("poly",
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width=0.150,
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spacing=0.210)
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# poly.8
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drc["poly_extend_active"] = 0.13
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# Not a rule
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drc["poly_to_contact"] = 0
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# poly.7 Minimum enclosure of active around gate
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drc["active_enclose_gate"] = 0.075
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# poly.4 Minimum spacing of field poly to active
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drc["poly_to_active"] = 0.075
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# poly.2 Minimum spacing of field poly
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drc["poly_to_field_poly"] = 0.210
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# difftap.1 Minimum width of active
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# difftap.3 Minimum spacing of active
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drc.add_layer("active",
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width=0.150,
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spacing=0.270)
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# difftap.8
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drc.add_enclosure("nwell",
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layer="active",
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enclosure=0.18,
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extension=0.18)
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# nsd/psd.5a
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drc.add_enclosure("implant",
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layer="active",
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enclosure=0.125)
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# Same as active enclosure?
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drc["implant_to_contact"] = 0.070
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# nsd/psd.1 nsd/psd.2
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drc.add_layer("implant",
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width=0.380,
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spacing=0.380,
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area=0.265)
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# licon.1, licon.2
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drc.add_layer("contact",
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width=0.170,
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spacing=0.170)
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# licon.5c (0.06 extension), (licon.7 for extension)
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drc.add_enclosure("active",
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layer="contact",
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enclosure=0.040,
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extension=0.060)
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# licon.7
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drc["tap_extend_contact"] = 0.120
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# licon.8 Minimum enclosure of poly around contact
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drc.add_enclosure("poly",
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layer="contact",
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enclosure=0.08,
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extension=0.08)
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# licon.11a
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drc["active_contact_to_gate"] = 0.050
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# npc.4 > licon.14 0.19 > licon.11a
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drc["poly_contact_to_gate"] = 0.270
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# licon.15
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drc["npc_enclose_poly"] = 0.1
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# li.1, li.3
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drc.add_layer("li",
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width=0.170,
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spacing=0.170)
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# licon.5
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drc.add_enclosure("li",
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layer="contact",
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enclosure=0,
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extension=0.080)
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drc.add_enclosure("li",
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layer="mcon",
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enclosure=0,
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extension=0.080)
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# mcon.1, mcon.2
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drc.add_layer("mcon",
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width=0.170,
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spacing=0.210)
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# m1.1 Minimum width of metal1
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# m1.2 Minimum spacing of metal1
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# m1.6 Minimum area of metal1
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drc.add_layer("m1",
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width=0.140,
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spacing=0.140,
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area=0.083)
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# m1.4 Minimum enclosure of metal1
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# m1.5 Minimum enclosure around contact on two opposite sides
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drc.add_enclosure("m1",
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layer="mcon",
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enclosure=0.030,
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extension=0.060)
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# via.4a Minimum enclosure around via1
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# via.5a Minimum enclosure around via1 on two opposite sides
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drc.add_enclosure("m1",
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layer="via1",
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enclosure=0.055,
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extension=0.085)
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# via.1a Minimum width of via1
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# via.2 Minimum spacing of via1
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drc.add_layer("via1",
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width=0.150,
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spacing=0.170)
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# m2.1 Minimum width of intermediate metal
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# m2.2 Minimum spacing of intermediate metal
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# m2.6 Minimum area of metal2
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drc.add_layer("m2",
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width=0.140,
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spacing=0.140,
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area=0.0676)
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# m2.4 Minimum enclosure around via1
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# m2.5 Minimum enclosure around via1 on two opposite sides
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drc.add_enclosure("m2",
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layer="via1",
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enclosure=0.055,
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extension=0.085)
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# via2.4 Minimum enclosure around via2
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# via2.5 Minimum enclosure around via2 on two opposite sides
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drc.add_enclosure("m2",
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layer="via2",
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enclosure=0.040,
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extension=0.085)
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# via2.1a Minimum width of Via2
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# via2.2 Minimum spacing of Via2
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drc.add_layer("via2",
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width=0.200,
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spacing=0.200)
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# m3.1 Minimum width of metal3
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# m3.2 Minimum spacing of metal3
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# m3.6 Minimum area of metal3
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drc.add_layer("m3",
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width=0.300,
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spacing=0.300,
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area=0.240)
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# m3.4 Minimum enclosure around via2
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drc.add_enclosure("m3",
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layer="via2",
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enclosure=0.065)
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# via3.4 Minimum enclosure around via3
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# via3.5 Minimum enclosure around via3 on two opposite sides
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drc.add_enclosure("m3",
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layer="via3",
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enclosure=0.060,
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extension=0.090)
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# via3.1 Minimum width of Via3
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# via3.2 Minimum spacing of Via3
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drc.add_layer("via3",
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width=0.200,
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spacing=0.200)
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# m4.1 Minimum width of metal4
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# m4.2 Minimum spacing of metal4
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# m4.7 Minimum area of metal4
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drc.add_layer("m4",
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width=0.300,
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spacing=0.300,
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area=0.240)
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# m4.3 Minimum enclosure around via3
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drc.add_enclosure("m4",
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layer="via3",
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enclosure=0.065)
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# FIXME: Wrong rule m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via4",
|
||||
enclosure=0.060)
|
||||
|
||||
|
||||
# via4.1 Minimum width of Via4
|
||||
# via4.2 Minimum spacing of Via4
|
||||
drc.add_layer("via4",
|
||||
width=0.800,
|
||||
spacing=0.800)
|
||||
|
||||
# FIXME: Wrong rules
|
||||
# m5.1 Minimum width of metal5
|
||||
# m5.2 Minimum spacing of metal5
|
||||
# m5.7 Minimum area of metal5
|
||||
drc.add_layer("m5",
|
||||
width=1.600,
|
||||
spacing=1.600,
|
||||
area=4.000)
|
||||
# m5.3 Minimum enclosure around via4
|
||||
drc.add_enclosure("m5",
|
||||
layer="via4",
|
||||
enclosure=0.310)
|
||||
|
||||
|
||||
|
||||
# Metal 5-10 are ommitted
|
||||
|
||||
###################################################
|
||||
# Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
# spice info
|
||||
spice = {}
|
||||
spice["nmos"] = "sky130_fd_pr__nfet_01v8"
|
||||
spice["pmos"] = "sky130_fd_pr__pfet_01v8"
|
||||
spice["power"]="vccd1"
|
||||
spice["ground"]="vssd1"
|
||||
|
||||
# whether or not the device model is actually a subckt
|
||||
spice["device_prefix"] = "X"
|
||||
|
||||
spice["fet_libraries"] = {"TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "tt"]]}
|
||||
|
||||
# spice stimulus related variables
|
||||
spice["feasible_period"] = 10 # estimated feasible period in ns
|
||||
spice["supply_voltages"] = [1.7, 1.8, 1.9] # Supply voltage corners in [Volts]
|
||||
spice["nom_supply_voltage"] = 1.8 # Nominal supply voltage in [Volts]
|
||||
spice["rise_time"] = 0.005 # rise time in [Nano-seconds]
|
||||
spice["fall_time"] = 0.005 # fall time in [Nano-seconds]
|
||||
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
|
||||
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
||||
|
||||
# analytical delay parameters
|
||||
spice["nom_threshold"] = 0.49 # Typical Threshold voltage in Volts
|
||||
spice["wire_unit_r"] = 0.125 # Unit wire resistance in ohms/square
|
||||
spice["wire_unit_c"] = 0.134 # Unit wire capacitance ff/um^2
|
||||
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
|
||||
spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff
|
||||
spice["dff_setup"] = 102.5391 # DFF setup time in ps
|
||||
spice["dff_hold"] = -56 # DFF hold time in ps
|
||||
spice["dff_in_cap"] = 6.89 # Input capacitance (D) [Femto-farad]
|
||||
spice["dff_out_cap"] = 6.89 # Output capacitance (Q) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
||||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["dff_leakage"] = 1 # Leakage power of flop in nW
|
||||
|
||||
spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
|
||||
|
||||
# Parameters related to sense amp enable timing and delay chain/RBL sizing
|
||||
parameter["le_tau"] = 2.25 # In pico-seconds.
|
||||
parameter["cap_relative_per_ff"] = 7.5 # Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["dff_clk_cin"] = 30.6 # relative capacitance
|
||||
parameter["6tcell_wl_cin"] = 3 # relative capacitance
|
||||
parameter["min_inv_para_delay"] = 2.4 # Tau delay units
|
||||
parameter["sa_en_pmos_size"] = 0.72 # micro-meters
|
||||
parameter["sa_en_nmos_size"] = 0.27 # micro-meters
|
||||
parameter["sa_inv_pmos_size"] = 0.54 # micro-meters
|
||||
parameter["sa_inv_nmos_size"] = 0.27 # micro-meters
|
||||
parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
# Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
if use_calibre:
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
elif use_klayout:
|
||||
drc_name = "klayout"
|
||||
lvs_name = "klayout"
|
||||
pex_name = "klayout"
|
||||
else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
Loading…
Reference in New Issue