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PEP8 Formatting

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mrg 2020-03-05 16:27:35 -08:00
parent 6506622dfb
commit 05f9e809b4
1 changed files with 66 additions and 84 deletions
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150
compiler/sram/sram_base.py
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@ -5,20 +5,16 @@
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.
# #
import sys
import datetime import datetime
import getpass
import debug import debug
from datetime import datetime
from importlib import reload from importlib import reload
from vector import vector from vector import vector
from globals import OPTS, print_time from globals import OPTS, print_time
import logical_effort
from design import design from design import design
from verilog import verilog from verilog import verilog
from lef import lef from lef import lef
from sram_factory import factory from sram_factory import factory
import logical_effort
class sram_base(design, verilog, lef): class sram_base(design, verilog, lef):
""" """
@ -36,11 +32,11 @@ class sram_base(design, verilog, lef):
self.bank_insts = [] self.bank_insts = []
if self.write_size: if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size) self.num_wmasks = int(self.word_size / self.write_size)
else: else:
self.num_wmasks = 0 self.num_wmasks = 0
#For logical effort delay calculations. # For logical effort delay calculations.
self.all_mods_except_control_done = False self.all_mods_except_control_done = False
def add_pins(self): def add_pins(self):
@ -48,11 +44,11 @@ class sram_base(design, verilog, lef):
for port in self.write_ports: for port in self.write_ports:
for bit in range(self.word_size): for bit in range(self.word_size):
self.add_pin("din{0}[{1}]".format(port,bit),"INPUT") self.add_pin("din{0}[{1}]".format(port, bit), "INPUT")
for port in self.all_ports: for port in self.all_ports:
for bit in range(self.addr_size): for bit in range(self.addr_size):
self.add_pin("addr{0}[{1}]".format(port,bit),"INPUT") self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT")
# These are used to create the physical pins # These are used to create the physical pins
self.control_logic_inputs = [] self.control_logic_inputs = []
@ -69,22 +65,21 @@ class sram_base(design, verilog, lef):
self.control_logic_outputs.append(self.control_logic_r.get_outputs()) self.control_logic_outputs.append(self.control_logic_r.get_outputs())
for port in self.all_ports: for port in self.all_ports:
self.add_pin("csb{}".format(port),"INPUT") self.add_pin("csb{}".format(port), "INPUT")
for port in self.readwrite_ports: for port in self.readwrite_ports:
self.add_pin("web{}".format(port),"INPUT") self.add_pin("web{}".format(port), "INPUT")
for port in self.all_ports: for port in self.all_ports:
self.add_pin("clk{}".format(port),"INPUT") self.add_pin("clk{}".format(port), "INPUT")
# add the optional write mask pins # add the optional write mask pins
for port in self.write_ports: for port in self.write_ports:
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
self.add_pin("wmask{0}[{1}]".format(port,bit),"INPUT") self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT")
for port in self.read_ports: for port in self.read_ports:
for bit in range(self.word_size): for bit in range(self.word_size):
self.add_pin("dout{0}[{1}]".format(port,bit),"OUTPUT") self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
self.add_pin("vdd","POWER") self.add_pin("vdd", "POWER")
self.add_pin("gnd","GROUND") self.add_pin("gnd", "GROUND")
def create_netlist(self): def create_netlist(self):
""" Netlist creation """ """ Netlist creation """
@ -100,23 +95,21 @@ class sram_base(design, verilog, lef):
self.width=0 self.width=0
self.height=0 self.height=0
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Submodules",datetime.now(), start_time) print_time("Submodules", datetime.now(), start_time)
def create_layout(self): def create_layout(self):
""" Layout creation """ """ Layout creation """
start_time = datetime.now() start_time = datetime.now()
self.place_instances() self.place_instances()
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Placement",datetime.now(), start_time) print_time("Placement", datetime.now(), start_time)
start_time = datetime.now() start_time = datetime.now()
self.route_layout() self.route_layout()
self.route_supplies() self.route_supplies()
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Routing",datetime.now(), start_time) print_time("Routing", datetime.now(), start_time)
self.add_lvs_correspondence_points() self.add_lvs_correspondence_points()
@ -130,10 +123,10 @@ class sram_base(design, verilog, lef):
# We only enable final verification if we have routed the design # We only enable final verification if we have routed the design
self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True)
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Verification",datetime.now(), start_time) print_time("Verification", datetime.now(), start_time)
def create_modules(self): def create_modules(self):
debug.error("Must override pure virtual function.",-1) debug.error("Must override pure virtual function.", -1)
def route_supplies(self): def route_supplies(self):
""" Route the supply grid and connect the pins to them. """ """ Route the supply grid and connect the pins to them. """
@ -141,8 +134,8 @@ class sram_base(design, verilog, lef):
# Copy the pins to the top level # Copy the pins to the top level
# This will either be used to route or left unconnected. # This will either be used to route or left unconnected.
for inst in self.insts: for inst in self.insts:
self.copy_power_pins(inst,"vdd") self.copy_power_pins(inst, "vdd")
self.copy_power_pins(inst,"gnd") self.copy_power_pins(inst, "gnd")
import tech import tech
if not OPTS.route_supplies: if not OPTS.route_supplies:
@ -164,33 +157,31 @@ class sram_base(design, verilog, lef):
from supply_grid_router import supply_grid_router as router from supply_grid_router import supply_grid_router as router
rtr=router(grid_stack, self) rtr=router(grid_stack, self)
rtr.route() rtr.route()
def compute_bus_sizes(self): def compute_bus_sizes(self):
""" Compute the independent bus widths shared between two and four bank SRAMs """ """ Compute the independent bus widths shared between two and four bank SRAMs """
# address size + control signals + one-hot bank select signals # address size + control signals + one-hot bank select signals
self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks,2) + 1 self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks, 2) + 1
# data bus size # data bus size
self.num_horizontal_line = self.word_size self.num_horizontal_line = self.word_size
self.vertical_bus_width = self.m2_pitch*self.num_vertical_line self.vertical_bus_width = self.m2_pitch * self.num_vertical_line
# vertical bus height depends on 2 or 4 banks # vertical bus height depends on 2 or 4 banks
self.data_bus_height = self.m3_pitch*self.num_horizontal_line self.data_bus_height = self.m3_pitch * self.num_horizontal_line
self.data_bus_width = 2*(self.bank.width + self.bank_to_bus_distance) + self.vertical_bus_width self.data_bus_width = 2 * (self.bank.width + self.bank_to_bus_distance) + self.vertical_bus_width
self.control_bus_height = self.m1_pitch*(self.control_size+2) self.control_bus_height = self.m1_pitch * (self.control_size + 2)
self.control_bus_width = self.bank.width + self.bank_to_bus_distance + self.vertical_bus_width self.control_bus_width = self.bank.width + self.bank_to_bus_distance + self.vertical_bus_width
self.supply_bus_height = self.m1_pitch*2 # 2 for vdd/gnd placed with control bus self.supply_bus_height = self.m1_pitch * 2 # 2 for vdd/gnd placed with control bus
self.supply_bus_width = self.data_bus_width self.supply_bus_width = self.data_bus_width
# Sanity check to ensure we can fit the control logic above a single bank (0.9 is a hack really) # Sanity check to ensure we can fit the control logic above a single bank (0.9 is a hack really)
debug.check(self.bank.width + self.vertical_bus_width > 0.9*self.control_logic.width, debug.check(self.bank.width + self.vertical_bus_width > 0.9 * self.control_logic.width,
"Bank is too small compared to control logic.") "Bank is too small compared to control logic.")
def add_busses(self): def add_busses(self):
""" Add the horizontal and vertical busses """ """ Add the horizontal and vertical busses """
# Vertical bus # Vertical bus
@ -213,24 +204,22 @@ class sram_base(design, verilog, lef):
names=self.control_bus_names[port], names=self.control_bus_names[port],
length=self.vertical_bus_height) length=self.vertical_bus_height)
self.addr_bus_names=["A{0}[{1}]".format(port,i) for i in range(self.addr_size)] self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.addr_size)]
self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2", self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
pitch=self.m2_pitch, pitch=self.m2_pitch,
offset=self.addr_bus_offset, offset=self.addr_bus_offset,
names=self.addr_bus_names, names=self.addr_bus_names,
length=self.addr_bus_height)) length=self.addr_bus_height))
self.bank_sel_bus_names = ["bank_sel{0}_{1}".format(port, i) for i in range(self.num_banks)]
self.bank_sel_bus_names = ["bank_sel{0}_{1}".format(port,i) for i in range(self.num_banks)]
self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2", self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
pitch=self.m2_pitch, pitch=self.m2_pitch,
offset=self.bank_sel_bus_offset, offset=self.bank_sel_bus_offset,
names=self.bank_sel_bus_names, names=self.bank_sel_bus_names,
length=self.vertical_bus_height)) length=self.vertical_bus_height))
# Horizontal data bus # Horizontal data bus
self.data_bus_names = ["DATA{0}[{1}]".format(port,i) for i in range(self.word_size)] self.data_bus_names = ["DATA{0}[{1}]".format(port, i) for i in range(self.word_size)]
self.data_bus_positions = self.create_horizontal_pin_bus(layer="m3", self.data_bus_positions = self.create_horizontal_pin_bus(layer="m3",
pitch=self.m3_pitch, pitch=self.m3_pitch,
offset=self.data_bus_offset, offset=self.data_bus_offset,
@ -249,7 +238,7 @@ class sram_base(design, verilog, lef):
# the decoder in 4-bank SRAMs # the decoder in 4-bank SRAMs
self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1", self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1",
pitch=self.m1_pitch, pitch=self.m1_pitch,
offset=self.supply_bus_offset+vector(0,self.m1_pitch), offset=self.supply_bus_offset + vector(0, self.m1_pitch),
names=["gnd"], names=["gnd"],
length=self.supply_bus_width)) length=self.supply_bus_width))
self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1", self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1",
@ -258,20 +247,17 @@ class sram_base(design, verilog, lef):
names=self.control_bus_names[port], names=self.control_bus_names[port],
length=self.control_bus_width)) length=self.control_bus_width))
def add_multi_bank_modules(self): def add_multi_bank_modules(self):
""" Create the multibank address flops and bank decoder """ """ Create the multibank address flops and bank decoder """
from dff_buf_array import dff_buf_array from dff_buf_array import dff_buf_array
self.msb_address = dff_buf_array(name="msb_address", self.msb_address = dff_buf_array(name="msb_address",
rows=1, rows=1,
columns=self.num_banks/2) columns=self.num_banks / 2)
self.add_mod(self.msb_address) self.add_mod(self.msb_address)
if self.num_banks>2: if self.num_banks>2:
self.msb_decoder = self.bank.decoder.pre2_4 self.msb_decoder = self.bank.decoder.pre2_4
self.add_mod(self.msb_decoder) self.add_mod(self.msb_decoder)
def add_modules(self): def add_modules(self):
self.bitcell = factory.create(module_type=OPTS.bitcell) self.bitcell = factory.create(module_type=OPTS.bitcell)
@ -293,7 +279,6 @@ class sram_base(design, verilog, lef):
if self.write_size: if self.write_size:
self.wmask_dff = factory.create("dff_array", module_name="wmask_dff", rows=1, columns=self.num_wmasks) self.wmask_dff = factory.create("dff_array", module_name="wmask_dff", rows=1, columns=self.num_wmasks)
self.add_mod(self.wmask_dff) self.add_mod(self.wmask_dff)
# Create the bank module (up to four are instantiated) # Create the bank module (up to four are instantiated)
self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank")
@ -305,7 +290,8 @@ class sram_base(design, verilog, lef):
self.bank_count = 0 self.bank_count = 0
#The control logic can resize itself based on the other modules. Requires all other modules added before control logic. # The control logic can resize itself based on the other modules.
# Requires all other modules added before control logic.
self.all_mods_except_control_done = True self.all_mods_except_control_done = True
c = reload(__import__(OPTS.control_logic)) c = reload(__import__(OPTS.control_logic))
@ -320,40 +306,40 @@ class sram_base(design, verilog, lef):
port_type="rw") port_type="rw")
self.add_mod(self.control_logic_rw) self.add_mod(self.control_logic_rw)
if len(self.writeonly_ports)>0: if len(self.writeonly_ports)>0:
self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row, words_per_row=self.words_per_row,
word_size=self.word_size, word_size=self.word_size,
sram=self, sram=self,
port_type="w") port_type="w")
self.add_mod(self.control_logic_w) self.add_mod(self.control_logic_w)
if len(self.readonly_ports)>0: if len(self.readonly_ports)>0:
self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row, words_per_row=self.words_per_row,
word_size=self.word_size, word_size=self.word_size,
sram=self, sram=self,
port_type="r") port_type="r")
self.add_mod(self.control_logic_r) self.add_mod(self.control_logic_r)
def create_bank(self,bank_num): def create_bank(self, bank_num):
""" Create a bank """ """ Create a bank """
self.bank_insts.append(self.add_inst(name="bank{0}".format(bank_num), self.bank_insts.append(self.add_inst(name="bank{0}".format(bank_num),
mod=self.bank)) mod=self.bank))
temp = [] temp = []
for port in self.read_ports: for port in self.read_ports:
for bit in range(self.word_size): for bit in range(self.word_size):
temp.append("dout{0}[{1}]".format(port,bit)) temp.append("dout{0}[{1}]".format(port, bit))
for port in self.all_ports: for port in self.all_ports:
temp.append("rbl_bl{0}".format(port)) temp.append("rbl_bl{0}".format(port))
for port in self.write_ports: for port in self.write_ports:
for bit in range(self.word_size): for bit in range(self.word_size):
temp.append("bank_din{0}[{1}]".format(port,bit)) temp.append("bank_din{0}[{1}]".format(port, bit))
for port in self.all_ports: for port in self.all_ports:
for bit in range(self.bank_addr_size): for bit in range(self.bank_addr_size):
temp.append("a{0}[{1}]".format(port,bit)) temp.append("a{0}[{1}]".format(port, bit))
if(self.num_banks > 1): if(self.num_banks > 1):
for port in self.all_ports: for port in self.all_ports:
temp.append("bank_sel{0}[{1}]".format(port,bank_num)) temp.append("bank_sel{0}[{1}]".format(port, bank_num))
for port in self.read_ports: for port in self.read_ports:
temp.append("s_en{0}".format(port)) temp.append("s_en{0}".format(port))
for port in self.all_ports: for port in self.all_ports:
@ -369,7 +355,6 @@ class sram_base(design, verilog, lef):
return self.bank_insts[-1] return self.bank_insts[-1]
def place_bank(self, bank_inst, position, x_flip, y_flip): def place_bank(self, bank_inst, position, x_flip, y_flip):
""" Place a bank at the given position with orientations """ """ Place a bank at the given position with orientations """
@ -400,7 +385,6 @@ class sram_base(design, verilog, lef):
return bank_inst return bank_inst
def create_row_addr_dff(self): def create_row_addr_dff(self):
""" Add all address flops for the main decoder """ """ Add all address flops for the main decoder """
insts = [] insts = []
@ -412,13 +396,12 @@ class sram_base(design, verilog, lef):
inputs = [] inputs = []
outputs = [] outputs = []
for bit in range(self.row_addr_size): for bit in range(self.row_addr_size):
inputs.append("addr{}[{}]".format(port,bit+self.col_addr_size)) inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size))
outputs.append("a{}[{}]".format(port,bit+self.col_addr_size)) outputs.append("a{}[{}]".format(port, bit + self.col_addr_size))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
return insts return insts
def create_col_addr_dff(self): def create_col_addr_dff(self):
""" Add and place all address flops for the column decoder """ """ Add and place all address flops for the column decoder """
@ -431,14 +414,13 @@ class sram_base(design, verilog, lef):
inputs = [] inputs = []
outputs = [] outputs = []
for bit in range(self.col_addr_size): for bit in range(self.col_addr_size):
inputs.append("addr{}[{}]".format(port,bit)) inputs.append("addr{}[{}]".format(port, bit))
outputs.append("a{}[{}]".format(port,bit)) outputs.append("a{}[{}]".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
return insts return insts
def create_data_dff(self): def create_data_dff(self):
""" Add and place all data flops """ """ Add and place all data flops """
insts = [] insts = []
@ -454,8 +436,8 @@ class sram_base(design, verilog, lef):
inputs = [] inputs = []
outputs = [] outputs = []
for bit in range(self.word_size): for bit in range(self.word_size):
inputs.append("din{}[{}]".format(port,bit)) inputs.append("din{}[{}]".format(port, bit))
outputs.append("bank_din{}[{}]".format(port,bit)) outputs.append("bank_din{}[{}]".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
@ -483,7 +465,6 @@ class sram_base(design, verilog, lef):
return insts return insts
def create_control_logic(self): def create_control_logic(self):
""" Add control logic instances """ """ Add control logic instances """
@ -516,12 +497,13 @@ class sram_base(design, verilog, lef):
return insts return insts
def connect_vbus_m2m3(self, src_pin, dest_pin): def connect_vbus_m2m3(self, src_pin, dest_pin):
""" Helper routine to connect an instance to a vertical bus. """
Helper routine to connect an instance to a vertical bus.
Routes horizontal then vertical L shape. Routes horizontal then vertical L shape.
Dest pin is assumed to be on M2. Dest pin is assumed to be on M2.
Src pin can be on M1/M2/M3.""" Src pin can be on M1/M2/M3.
"""
if src_pin.cx()<dest_pin.cx(): if src_pin.cx()<dest_pin.cx():
in_pos = src_pin.rc() in_pos = src_pin.rc()
@ -533,16 +515,17 @@ class sram_base(design, verilog, lef):
out_pos = dest_pin.uc() out_pos = dest_pin.uc()
# move horizontal first # move horizontal first
self.add_wire(("m3","via2","m2"),[in_pos, vector(out_pos.x,in_pos.y),out_pos]) self.add_wire(("m3", "via2", "m2"),
[in_pos,
vector(out_pos.x, in_pos.y),
out_pos])
if src_pin.layer=="m1": if src_pin.layer=="m1":
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=in_pos) offset=in_pos)
if src_pin.layer in ["m1","m2"]: if src_pin.layer in ["m1", "m2"]:
self.add_via_center(layers=self.m2_stack, self.add_via_center(layers=self.m2_stack,
offset=in_pos) offset=in_pos)
def sp_write(self, sp_name): def sp_write(self, sp_name):
# Write the entire spice of the object to the file # Write the entire spice of the object to the file
############################################################ ############################################################
@ -571,40 +554,39 @@ class sram_base(design, verilog, lef):
"""Get the all the stage efforts for each stage in the path from clk_buf to a wordline""" """Get the all the stage efforts for each stage in the path from clk_buf to a wordline"""
stage_effort_list = [] stage_effort_list = []
#Clk_buf originates from the control logic so only the bank is related to the wordline path # Clk_buf originates from the control logic so only the bank is related to the wordline path
external_wordline_cout = 0 #No loading on the wordline other than in the bank. # No loading on the wordline other than in the bank.
external_wordline_cout = 0
stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout, inp_is_rise) stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout, inp_is_rise)
return stage_effort_list return stage_effort_list
def get_wl_en_cin(self): def get_wl_en_cin(self):
"""Gets the capacitive load the of clock (clk_buf) for the sram""" """Gets the capacitive load the of clock (clk_buf) for the sram"""
#Only the wordline drivers within the bank use this signal # Only the wordline drivers within the bank use this signal
return self.bank.get_wl_en_cin() return self.bank.get_wl_en_cin()
def get_w_en_cin(self): def get_w_en_cin(self):
"""Gets the capacitive load the of write enable (w_en) for the sram""" """Gets the capacitive load the of write enable (w_en) for the sram"""
#Only the write drivers within the bank use this signal # Only the write drivers within the bank use this signal
return self.bank.get_w_en_cin() return self.bank.get_w_en_cin()
def get_p_en_bar_cin(self): def get_p_en_bar_cin(self):
"""Gets the capacitive load the of precharge enable (p_en_bar) for the sram""" """Gets the capacitive load the of precharge enable (p_en_bar) for the sram"""
#Only the precharges within the bank use this signal # Only the precharges within the bank use this signal
return self.bank.get_p_en_bar_cin() return self.bank.get_p_en_bar_cin()
def get_clk_bar_cin(self): def get_clk_bar_cin(self):
"""Gets the capacitive load the of clock (clk_buf_bar) for the sram""" """Gets the capacitive load the of clock (clk_buf_bar) for the sram"""
#As clk_buf_bar is an output of the control logic. The cap for that module is not determined here. # As clk_buf_bar is an output of the control logic. The cap for that module is not determined here.
#Only the precharge cells use this signal (other than the control logic) # Only the precharge cells use this signal (other than the control logic)
return self.bank.get_clk_bar_cin() return self.bank.get_clk_bar_cin()
def get_sen_cin(self): def get_sen_cin(self):
"""Gets the capacitive load the of sense amp enable for the sram""" """Gets the capacitive load the of sense amp enable for the sram"""
#Only the sense_amps use this signal (other than the control logic) # Only the sense_amps use this signal (other than the control logic)
return self.bank.get_sen_cin() return self.bank.get_sen_cin()
def get_dff_clk_buf_cin(self): def get_dff_clk_buf_cin(self):
"""Get the relative capacitance of the clk_buf signal. """Get the relative capacitance of the clk_buf signal.
Does not get the control logic loading but everything else""" Does not get the control logic loading but everything else"""