mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 11:08:01 +02:00
move sky130 specific stuff to tech module lib
This commit is contained in:
jcirimel
@@ -147,78 +147,37 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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self.add_mod(self.dummy_row)
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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# Dummy Row or Col Cap, depending on bitcell array properties
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col_cap_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
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self.col_cap = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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self.add_mod(self.col_cap)
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# Dummy Col or Row Cap, depending on bitcell array properties
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row_cap_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array")
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) % 2)
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self.add_mod(self.row_cap_left)
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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# dummy column
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) %2)
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self.add_mod(self.row_cap_right)
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else:
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# Dummy Row or Col Cap, depending on bitcell array properties
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col_cap_module_type = ("s8_col_cap_array" if end_caps_enabled else "dummy_array")
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self.col_cap_top = factory.create(module_type=col_cap_module_type,
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# Dummy Row or Col Cap, depending on bitcell array properties
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col_cap_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
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self.col_cap = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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# dummy column + left replica column
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column_offset=1 + len(self.left_rbl),
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mirror=0,
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location="top")
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self.add_mod(self.col_cap_top)
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mirror=0)
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self.add_mod(self.col_cap)
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self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + len(self.left_rbl),
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mirror=0,
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location="bottom")
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self.add_mod(self.col_cap_bottom)
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# Dummy Col or Row Cap, depending on bitcell array properties
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row_cap_module_type = ("s8_row_cap_array" if end_caps_enabled else "dummy_array")
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# Dummy Col or Row Cap, depending on bitcell array properties
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row_cap_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array")
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=0)
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self.add_mod(self.row_cap_left)
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) % 2)
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self.add_mod(self.row_cap_left)
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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# dummy column
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=0)
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self.add_mod(self.row_cap_right)
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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# dummy column
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) %2)
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self.add_mod(self.row_cap_right)
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def add_pins(self):
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@@ -279,15 +238,13 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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@@ -297,56 +254,51 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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def create_instances(self):
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""" Create the module instances used in this design """
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.supplies = ["vdd", "gnd"]
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self.supplies = ["vdd", "gnd"]
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# Used for names/dimensions only
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self.cell = factory.create(module_type="bitcell")
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# Used for names/dimensions only
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self.cell = factory.create(module_type="bitcell")
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap))
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self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap))
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self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap))
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self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap))
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self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
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mod=self.row_cap_left))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
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mod=self.row_cap_right))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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else:
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from tech import custom_replica_bitcell_array_arrangement
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custom_replica_bitcell_array_arrangement(self)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
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mod=self.row_cap_left))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
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mod=self.row_cap_right))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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def create_layout(self):
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@@ -357,26 +309,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.unused_offset = vector(self.unused_pitch, 0)
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# Add extra width on the left and right for the unused WLs
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.height = (self.row_size + self.extra_rows) * self.dummy_row.height
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self.width = (self.column_size + self.extra_cols) * self.cell.width + 2 * self.unused_pitch
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else:
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self.width = self.row_cap_left.width + self.row_cap_right.width + self.col_cap_top.width
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for rbl in range(self.rbl[0] + self.rbl[1]):
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self.width += self.replica_col_insts[rbl].width
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self.height = self.row_cap_left.height
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self.height = (self.row_size + self.extra_rows) * self.dummy_row.height
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self.width = (self.column_size + self.extra_cols) * self.cell.width + 2 * self.unused_pitch
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.strap_offset = vector(0, 0)
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self.col_end_offset = vector(self.cell.width, self.cell.height)
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self.row_end_offset = vector(self.cell.width, self.cell.height)
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else:
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self.strap_offset = vector(self.replica_col_insts[0].mod.strap1.width, self.replica_col_insts[0].mod.strap1.height)
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self.col_end_offset = vector(self.dummy_row_insts[0].mod.colend1.width, self.dummy_row_insts[0].mod.colend1.height)
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self.row_end_offset = vector(self.dummy_col_insts[0].mod.rowend1.width, self.dummy_col_insts[0].mod.rowend1.height)
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self.strap_offset = vector(0, 0)
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self.col_end_offset = vector(self.cell.width, self.cell.height)
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self.row_end_offset = vector(self.cell.width, self.cell.height)
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# Everything is computed with the main array at (self.unused_pitch, 0) to start
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self.bitcell_array_inst.place(offset=self.unused_offset)
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@@ -503,50 +444,28 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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#All wordlines
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#Main array wl and bl/br
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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for pin_name in self.all_wordline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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# Replica wordlines (go by the row instead of replica column because we may have to add a pin
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# even though the column is in another local bitcell array)
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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continue
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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else:
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for pin_name in self.all_wordline_names:
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pin_list = self.dummy_col_insts[0].get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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# Replica wordlines (go by the row instead of replica column because we may have to add a pin
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# even though the column is in another local bitcell array)
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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continue
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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for pin_name in self.all_wordline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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# Replica wordlines (go by the row instead of replica column because we may have to add a pin
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# even though the column is in another local bitcell array)
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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continue
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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for pin_name in self.all_bitline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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@@ -603,17 +522,16 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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def route_unused_wordlines(self):
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""" Connect the unused RBL and dummy wordlines to gnd """
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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# This grounds all the dummy row word lines
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for inst in self.dummy_row_insts:
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for wl_name in self.col_cap.get_wordline_names():
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self.ground_pin(inst, wl_name)
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# This grounds all the dummy row word lines
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for inst in self.dummy_row_insts:
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for wl_name in self.col_cap.get_wordline_names():
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self.ground_pin(inst, wl_name)
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# Ground the unused replica wordlines
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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self.ground_pin(inst, pin_name)
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# Ground the unused replica wordlines
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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self.ground_pin(inst, pin_name)
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|
||||
def ground_pin(self, inst, name):
|
||||
pin = inst.get_pin(name)
|
||||
|
||||
Reference in New Issue
Block a user