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move sky130 specific stuff to tech module lib

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This commit is contained in:
jcirimel
2020-10-13 04:48:10 -07:00
parent c3d6be27be
commit 05667d784f
14 changed files with 256 additions and 1136 deletions
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compiler/modules/dummy_array.py
+13 -32
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@@ -45,31 +45,19 @@ class dummy_array(bitcell_base_array):
def add_modules(self):
""" Add the modules used in this design """
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
self.cell = factory.create(module_type="bitcell")
else:
self.dummy_cell = factory.create(module_type="s8_bitcell", version = "opt1")
self.dummy_cell2 = factory.create(module_type="s8_bitcell", version = "opt1a")
self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
self.add_mod(self.dummy_cell2)
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
self.cell = factory.create(module_type="bitcell")
self.add_mod(self.dummy_cell)
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.dummy_cell)
self.connect_inst(self.get_bitcell_pins(row, col))
else:
from tech import custom_cell_arrangement
custom_cell_arrangement(self)
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.dummy_cell)
self.connect_inst(self.get_bitcell_pins(row, col))
def add_pins(self):
# bitline pins are not added because they are floating
@@ -119,18 +107,11 @@ class dummy_array(bitcell_base_array):
height=wl_pin.height())
# Copy a vdd/gnd layout pin from every cell
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
else:
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row, col]
for pin_name in ["vpwr", "vgnd"]:
self.copy_layout_pin(inst, pin_name)
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
def input_load(self):