mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 02:57:53 +02:00
move sky130 specific stuff to tech module lib
This commit is contained in:
jcirimel
@@ -7,7 +7,6 @@
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#
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import debug
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from bitcell_base_array import bitcell_base_array
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from s8_corner import s8_corner
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from tech import drc, spice
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from tech import cell_properties as props
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from globals import OPTS
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@@ -54,31 +53,18 @@ class bitcell_array(bitcell_base_array):
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def add_modules(self):
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""" Add the modules used in this design """
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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self.cell = factory.create(module_type="bitcell")
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self.add_mod(self.cell)
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else:
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self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
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self.add_mod(self.cell)
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self.add_mod(factory.create(module_type="s8_bitcell", version = "opt1a"))
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self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
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self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
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self.cell = factory.create(module_type="bitcell")
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self.add_mod(self.cell)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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else:
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from tech import custom_cell_arrangement
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custom_cell_arrangement(self)
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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@@ -25,13 +25,8 @@ class bitcell_base_array(design.design):
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self.column_offset = column_offset
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# Bitcell for port names only
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.cell = factory.create(module_type="bitcell")
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else:
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self.cell = factory.create(module_type="s8_bitcell", version="opt1")
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self.cell2 = factory.create(module_type="s8_bitcell", version="opt1a")
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self.strap = factory.create(module_type="s8_internal", version="wlstrap")
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self.strap2 = factory.create(module_type="s8_internal", version="wlstrap_p")
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self.cell = factory.create(module_type="bitcell")
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self.wordline_names = [[] for port in self.all_ports]
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self.all_wordline_names = []
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@@ -72,12 +67,9 @@ class bitcell_base_array(design.design):
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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else:
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self.add_pin("vpwr", "POWER")
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self.add_pin("vgnd", "GROUND")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def get_bitcell_pins(self, row, col):
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""" Creates a list of connections in the bitcell,
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@@ -173,24 +165,13 @@ class bitcell_base_array(design.design):
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width=self.width,
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height=wl_pin.height())
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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else:
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vpwr", "vgnd"]:
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self.copy_layout_pin(inst, pin_name)
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def _adjust_x_offset(self, xoffset, col, col_offset):
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tempx = xoffset
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dir_y = False
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@@ -210,35 +191,31 @@ class bitcell_base_array(design.design):
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return (tempy, dir_x)
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def place_array(self, name_template, row_offset=0):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = 0.0
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = 0.0
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(self.row_size):
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tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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for row in range(self.row_size):
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tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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else:
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from tech import custom_cell_placement
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custom_cell_placement(self)
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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def get_column_offsets(self):
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"""
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@@ -45,31 +45,19 @@ class dummy_array(bitcell_base_array):
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def add_modules(self):
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""" Add the modules used in this design """
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
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self.cell = factory.create(module_type="bitcell")
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else:
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self.dummy_cell = factory.create(module_type="s8_bitcell", version = "opt1")
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self.dummy_cell2 = factory.create(module_type="s8_bitcell", version = "opt1a")
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self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
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self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
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self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
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self.add_mod(self.dummy_cell2)
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self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
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self.cell = factory.create(module_type="bitcell")
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self.add_mod(self.dummy_cell)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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else:
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from tech import custom_cell_arrangement
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custom_cell_arrangement(self)
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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def add_pins(self):
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# bitline pins are not added because they are floating
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@@ -119,18 +107,11 @@ class dummy_array(bitcell_base_array):
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height=wl_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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else:
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vpwr", "vgnd"]:
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self.copy_layout_pin(inst, pin_name)
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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def input_load(self):
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@@ -147,78 +147,37 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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self.add_mod(self.dummy_row)
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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# Dummy Row or Col Cap, depending on bitcell array properties
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col_cap_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
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self.col_cap = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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self.add_mod(self.col_cap)
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# Dummy Col or Row Cap, depending on bitcell array properties
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row_cap_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array")
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) % 2)
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self.add_mod(self.row_cap_left)
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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# dummy column
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) %2)
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self.add_mod(self.row_cap_right)
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else:
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# Dummy Row or Col Cap, depending on bitcell array properties
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col_cap_module_type = ("s8_col_cap_array" if end_caps_enabled else "dummy_array")
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self.col_cap_top = factory.create(module_type=col_cap_module_type,
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# Dummy Row or Col Cap, depending on bitcell array properties
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col_cap_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
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self.col_cap = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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# dummy column + left replica column
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column_offset=1 + len(self.left_rbl),
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mirror=0,
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location="top")
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self.add_mod(self.col_cap_top)
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mirror=0)
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self.add_mod(self.col_cap)
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self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + len(self.left_rbl),
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mirror=0,
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location="bottom")
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self.add_mod(self.col_cap_bottom)
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# Dummy Col or Row Cap, depending on bitcell array properties
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row_cap_module_type = ("s8_row_cap_array" if end_caps_enabled else "dummy_array")
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# Dummy Col or Row Cap, depending on bitcell array properties
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row_cap_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array")
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=0)
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self.add_mod(self.row_cap_left)
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) % 2)
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self.add_mod(self.row_cap_left)
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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# dummy column
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=0)
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self.add_mod(self.row_cap_right)
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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# dummy column
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) %2)
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self.add_mod(self.row_cap_right)
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def add_pins(self):
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@@ -279,15 +238,13 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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@@ -297,56 +254,51 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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def create_instances(self):
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""" Create the module instances used in this design """
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.supplies = ["vdd", "gnd"]
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self.supplies = ["vdd", "gnd"]
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# Used for names/dimensions only
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self.cell = factory.create(module_type="bitcell")
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# Used for names/dimensions only
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self.cell = factory.create(module_type="bitcell")
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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||||
else:
|
||||
self.replica_col_insts.append(None)
|
||||
|
||||
# Dummy rows under the bitcell array (connected with with the replica cell wl)
|
||||
self.dummy_row_replica_insts = []
|
||||
# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
|
||||
for port in self.all_ports:
|
||||
self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
|
||||
mod=self.dummy_row))
|
||||
self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
|
||||
|
||||
# Replica columns
|
||||
self.replica_col_insts = []
|
||||
for port in self.all_ports:
|
||||
if port in self.rbls:
|
||||
self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
|
||||
mod=self.replica_columns[port]))
|
||||
self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
|
||||
else:
|
||||
self.replica_col_insts.append(None)
|
||||
|
||||
# Dummy rows under the bitcell array (connected with with the replica cell wl)
|
||||
self.dummy_row_replica_insts = []
|
||||
# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
|
||||
for port in self.all_ports:
|
||||
self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
|
||||
mod=self.dummy_row))
|
||||
self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
|
||||
# Top/bottom dummy rows or col caps
|
||||
self.dummy_row_insts = []
|
||||
self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
|
||||
mod=self.col_cap))
|
||||
self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
|
||||
self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
|
||||
mod=self.col_cap))
|
||||
self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
|
||||
|
||||
# Top/bottom dummy rows or col caps
|
||||
self.dummy_row_insts = []
|
||||
self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
|
||||
mod=self.col_cap))
|
||||
self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
|
||||
self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
|
||||
mod=self.col_cap))
|
||||
self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
|
||||
|
||||
# Left/right Dummy columns
|
||||
self.dummy_col_insts = []
|
||||
self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
|
||||
mod=self.row_cap_left))
|
||||
self.connect_inst(self.replica_array_wordline_names + self.supplies)
|
||||
self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
|
||||
mod=self.row_cap_right))
|
||||
self.connect_inst(self.replica_array_wordline_names + self.supplies)
|
||||
else:
|
||||
from tech import custom_replica_bitcell_array_arrangement
|
||||
custom_replica_bitcell_array_arrangement(self)
|
||||
# Left/right Dummy columns
|
||||
self.dummy_col_insts = []
|
||||
self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
|
||||
mod=self.row_cap_left))
|
||||
self.connect_inst(self.replica_array_wordline_names + self.supplies)
|
||||
self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
|
||||
mod=self.row_cap_right))
|
||||
self.connect_inst(self.replica_array_wordline_names + self.supplies)
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
@@ -357,26 +309,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
self.unused_offset = vector(self.unused_pitch, 0)
|
||||
|
||||
# Add extra width on the left and right for the unused WLs
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
self.height = (self.row_size + self.extra_rows) * self.dummy_row.height
|
||||
self.width = (self.column_size + self.extra_cols) * self.cell.width + 2 * self.unused_pitch
|
||||
else:
|
||||
self.width = self.row_cap_left.width + self.row_cap_right.width + self.col_cap_top.width
|
||||
for rbl in range(self.rbl[0] + self.rbl[1]):
|
||||
self.width += self.replica_col_insts[rbl].width
|
||||
self.height = self.row_cap_left.height
|
||||
self.height = (self.row_size + self.extra_rows) * self.dummy_row.height
|
||||
self.width = (self.column_size + self.extra_cols) * self.cell.width + 2 * self.unused_pitch
|
||||
|
||||
|
||||
# This is a bitcell x bitcell offset to scale
|
||||
self.bitcell_offset = vector(self.cell.width, self.cell.height)
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
self.strap_offset = vector(0, 0)
|
||||
self.col_end_offset = vector(self.cell.width, self.cell.height)
|
||||
self.row_end_offset = vector(self.cell.width, self.cell.height)
|
||||
else:
|
||||
self.strap_offset = vector(self.replica_col_insts[0].mod.strap1.width, self.replica_col_insts[0].mod.strap1.height)
|
||||
self.col_end_offset = vector(self.dummy_row_insts[0].mod.colend1.width, self.dummy_row_insts[0].mod.colend1.height)
|
||||
self.row_end_offset = vector(self.dummy_col_insts[0].mod.rowend1.width, self.dummy_col_insts[0].mod.rowend1.height)
|
||||
self.strap_offset = vector(0, 0)
|
||||
self.col_end_offset = vector(self.cell.width, self.cell.height)
|
||||
self.row_end_offset = vector(self.cell.width, self.cell.height)
|
||||
|
||||
# Everything is computed with the main array at (self.unused_pitch, 0) to start
|
||||
self.bitcell_array_inst.place(offset=self.unused_offset)
|
||||
@@ -503,50 +444,28 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
|
||||
#All wordlines
|
||||
#Main array wl and bl/br
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
|
||||
for pin_name in self.all_wordline_names:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
# Replica wordlines (go by the row instead of replica column because we may have to add a pin
|
||||
# even though the column is in another local bitcell array)
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
continue
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
else:
|
||||
for pin_name in self.all_wordline_names:
|
||||
pin_list = self.dummy_col_insts[0].get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
# Replica wordlines (go by the row instead of replica column because we may have to add a pin
|
||||
# even though the column is in another local bitcell array)
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
continue
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in self.all_wordline_names:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
# Replica wordlines (go by the row instead of replica column because we may have to add a pin
|
||||
# even though the column is in another local bitcell array)
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
continue
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in self.all_bitline_names:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
@@ -603,17 +522,16 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
|
||||
def route_unused_wordlines(self):
|
||||
""" Connect the unused RBL and dummy wordlines to gnd """
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
# This grounds all the dummy row word lines
|
||||
for inst in self.dummy_row_insts:
|
||||
for wl_name in self.col_cap.get_wordline_names():
|
||||
self.ground_pin(inst, wl_name)
|
||||
# This grounds all the dummy row word lines
|
||||
for inst in self.dummy_row_insts:
|
||||
for wl_name in self.col_cap.get_wordline_names():
|
||||
self.ground_pin(inst, wl_name)
|
||||
|
||||
# Ground the unused replica wordlines
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
self.ground_pin(inst, pin_name)
|
||||
# Ground the unused replica wordlines
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
self.ground_pin(inst, pin_name)
|
||||
|
||||
def ground_pin(self, inst, name):
|
||||
pin = inst.get_pin(name)
|
||||
|
||||
+102
-172
@@ -28,10 +28,8 @@ class replica_column(bitcell_base_array):
|
||||
self.right_rbl = rbl[1]
|
||||
self.replica_bit = replica_bit
|
||||
# left, right, regular rows plus top/bottom dummy cells
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
self.total_size = self.left_rbl + rows + self.right_rbl + 2
|
||||
else:
|
||||
self.total_size = self.left_rbl + rows + self.right_rbl + 2
|
||||
self.total_size = self.left_rbl + rows + self.right_rbl + 2
|
||||
|
||||
self.column_offset = column_offset
|
||||
|
||||
debug.check(replica_bit != 0 and replica_bit != rows,
|
||||
@@ -80,197 +78,129 @@ class replica_column(bitcell_base_array):
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_modules(self):
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
self.replica_cell = factory.create(module_type="replica_{}".format(OPTS.bitcell))
|
||||
self.add_mod(self.replica_cell)
|
||||
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
|
||||
self.add_mod(self.dummy_cell)
|
||||
try:
|
||||
edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy")
|
||||
except AttributeError:
|
||||
edge_module_type = "dummy"
|
||||
self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell)
|
||||
self.add_mod(self.edge_cell)
|
||||
# Used for pin names only
|
||||
self.cell = factory.create(module_type="bitcell")
|
||||
else:
|
||||
self.replica_cell = factory.create(module_type="s8_bitcell", version = "opt1")
|
||||
self.add_mod(self.replica_cell)
|
||||
self.cell = self.replica_cell
|
||||
self.replica_cell2 = factory.create(module_type="s8_bitcell", version = "opt1a")
|
||||
self.add_mod(self.replica_cell2)
|
||||
self.replica_cell = factory.create(module_type="replica_{}".format(OPTS.bitcell))
|
||||
self.add_mod(self.replica_cell)
|
||||
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
|
||||
self.add_mod(self.dummy_cell)
|
||||
try:
|
||||
edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy")
|
||||
except AttributeError:
|
||||
edge_module_type = "dummy"
|
||||
self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell)
|
||||
self.add_mod(self.edge_cell)
|
||||
# Used for pin names only
|
||||
self.cell = factory.create(module_type="bitcell")
|
||||
|
||||
self.dummy_cell = factory.create(module_type="s8_bitcell", version = "opt1")
|
||||
self.dummy_cell2 = factory.create(module_type="s8_bitcell", version = "opt1")
|
||||
|
||||
self.strap1 = factory.create(module_type="s8_internal", version = "wlstrap")
|
||||
self.add_mod(self.strap1)
|
||||
self.strap2 = factory.create(module_type="s8_internal", version = "wlstrap_p")
|
||||
self.add_mod(self.strap2)
|
||||
|
||||
self.colend = factory.create(module_type="s8_col_end", version = "colenda")
|
||||
self.edge_cell = self.colend
|
||||
self.add_mod(self.colend)
|
||||
self.colenda = factory.create(module_type="s8_col_end", version = "colenda")
|
||||
self.add_mod(self.colenda)
|
||||
self.colend_p_cent = factory.create(module_type="s8_col_end", version = "colend_p_cent")
|
||||
self.add_mod(self.colend_p_cent)
|
||||
self.colenda_p_cent = factory.create(module_type="s8_col_end", version = "colenda_p_cent")
|
||||
self.add_mod(self.colenda_p_cent)
|
||||
|
||||
def create_instances(self):
|
||||
self.cell_inst = {}
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
try:
|
||||
end_caps_enabled = cell_properties.bitcell.end_caps
|
||||
except AttributeError:
|
||||
end_caps_enabled = False
|
||||
|
||||
for row in range(self.total_size):
|
||||
name="rbc_{0}".format(row)
|
||||
# Top/bottom cell are always dummy cells.
|
||||
# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
|
||||
# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
|
||||
if (row > self.left_rbl and row < self.total_size - self.right_rbl - 1):
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.replica_cell)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
elif row==self.replica_bit:
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.replica_cell)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
elif (row == 0 or row == self.total_size - 1):
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.edge_cell)
|
||||
if end_caps_enabled:
|
||||
self.connect_inst(self.get_bitcell_pins_col_cap(row, 0))
|
||||
else:
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
try:
|
||||
end_caps_enabled = cell_properties.bitcell.end_caps
|
||||
except AttributeError:
|
||||
end_caps_enabled = False
|
||||
|
||||
for row in range(self.total_size):
|
||||
name="rbc_{0}".format(row)
|
||||
# Top/bottom cell are always dummy cells.
|
||||
# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
|
||||
# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
|
||||
if (row > self.left_rbl and row < self.total_size - self.right_rbl - 1):
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.replica_cell)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
elif row==self.replica_bit:
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.replica_cell)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
elif (row == 0 or row == self.total_size - 1):
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.edge_cell)
|
||||
if end_caps_enabled:
|
||||
self.connect_inst(self.get_bitcell_pins_col_cap(row, 0))
|
||||
else:
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.dummy_cell)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
else:
|
||||
from tech import custom_replica_column_arrangement
|
||||
custom_replica_column_arrangement(self)
|
||||
else:
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.dummy_cell)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
|
||||
def place_instances(self):
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
# Flip the mirrors if we have an odd number of replica+dummy rows at the bottom
|
||||
# so that we will start with mirroring rather than not mirroring
|
||||
rbl_offset = (self.left_rbl + 1) %2
|
||||
|
||||
# Flip the mirrors if we have an odd number of replica+dummy rows at the bottom
|
||||
# so that we will start with mirroring rather than not mirroring
|
||||
rbl_offset = (self.left_rbl + 1) %2
|
||||
# if our bitcells are mirrored on the y axis, check if we are in global
|
||||
# column that needs to be flipped.
|
||||
dir_y = False
|
||||
xoffset = 0
|
||||
if cell_properties.bitcell.mirror.y and self.column_offset % 2:
|
||||
dir_y = True
|
||||
xoffset = self.replica_cell.width
|
||||
|
||||
# if our bitcells are mirrored on the y axis, check if we are in global
|
||||
# column that needs to be flipped.
|
||||
dir_y = False
|
||||
xoffset = 0
|
||||
if cell_properties.bitcell.mirror.y and self.column_offset % 2:
|
||||
dir_y = True
|
||||
xoffset = self.replica_cell.width
|
||||
for row in range(self.total_size):
|
||||
# name = "bit_r{0}_{1}".format(row, "rbl")
|
||||
dir_x = cell_properties.bitcell.mirror.x and (row + rbl_offset) % 2
|
||||
|
||||
for row in range(self.total_size):
|
||||
# name = "bit_r{0}_{1}".format(row, "rbl")
|
||||
dir_x = cell_properties.bitcell.mirror.x and (row + rbl_offset) % 2
|
||||
offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2))
|
||||
|
||||
offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2))
|
||||
if dir_x and dir_y:
|
||||
dir_key = "XY"
|
||||
elif dir_x:
|
||||
dir_key = "MX"
|
||||
elif dir_y:
|
||||
dir_key = "MY"
|
||||
else:
|
||||
dir_key = ""
|
||||
|
||||
if dir_x and dir_y:
|
||||
dir_key = "XY"
|
||||
elif dir_x:
|
||||
dir_key = "MX"
|
||||
elif dir_y:
|
||||
dir_key = "MY"
|
||||
else:
|
||||
dir_key = ""
|
||||
self.cell_inst[row].place(offset=offset,
|
||||
mirror=dir_key)
|
||||
|
||||
self.cell_inst[row].place(offset=offset,
|
||||
mirror=dir_key)
|
||||
else:
|
||||
from tech import custom_replica_cell_placement
|
||||
custom_replica_cell_placement(self)
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
for port in self.all_ports:
|
||||
bl_pin = self.cell_inst[0].get_pin(self.cell.get_bl_name(port))
|
||||
self.add_layout_pin(text="bl_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
bl_pin = self.cell_inst[0].get_pin(self.cell.get_br_name(port))
|
||||
self.add_layout_pin(text="br_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
|
||||
try:
|
||||
end_caps_enabled = cell_properties.bitcell.end_caps
|
||||
except AttributeError:
|
||||
end_caps_enabled = False
|
||||
|
||||
if end_caps_enabled:
|
||||
row_range_max = self.total_size - 1
|
||||
row_range_min = 1
|
||||
else:
|
||||
row_range_max = self.total_size
|
||||
row_range_min = 0
|
||||
|
||||
for port in self.all_ports:
|
||||
for row in range(row_range_min, row_range_max):
|
||||
wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
|
||||
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# Supplies are only connected in the ends
|
||||
for (index, inst) in self.cell_inst.items():
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
|
||||
self.copy_power_pins(inst, pin_name)
|
||||
else:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
else:
|
||||
for port in self.all_ports:
|
||||
bl_pin = self.cell_inst[2].get_pin(self.cell.get_bl_name(port))
|
||||
self.add_layout_pin(text="bl_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
bl_pin = self.cell_inst[2].get_pin(self.cell.get_br_name(port))
|
||||
self.add_layout_pin(text="br_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
for port in self.all_ports:
|
||||
bl_pin = self.cell_inst[0].get_pin(self.cell.get_bl_name(port))
|
||||
self.add_layout_pin(text="bl_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
bl_pin = self.cell_inst[0].get_pin(self.cell.get_br_name(port))
|
||||
self.add_layout_pin(text="br_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
|
||||
try:
|
||||
end_caps_enabled = cell_properties.bitcell.end_caps
|
||||
except AttributeError:
|
||||
end_caps_enabled = False
|
||||
|
||||
if end_caps_enabled:
|
||||
row_range_max = self.total_size - 1
|
||||
row_range_min = 1
|
||||
else:
|
||||
row_range_max = self.total_size
|
||||
row_range_min = 0
|
||||
|
||||
for port in self.all_ports:
|
||||
for row in range(row_range_min, row_range_max):
|
||||
wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
|
||||
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# Supplies are only connected in the ends
|
||||
for (index, inst) in self.cell_inst.items():
|
||||
for pin_name in ["vpwr", "vgnd"]:
|
||||
if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
|
||||
self.copy_power_pins(inst, pin_name)
|
||||
else:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
for port in self.all_ports:
|
||||
for row in range(row_range_min, row_range_max):
|
||||
wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
|
||||
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# Supplies are only connected in the ends
|
||||
for (index, inst) in self.cell_inst.items():
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
|
||||
self.copy_power_pins(inst, pin_name)
|
||||
else:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
|
||||
def get_bitline_names(self, port=None):
|
||||
if port == None:
|
||||
return self.all_bitline_names
|
||||
|
||||
Reference in New Issue
Block a user