mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed code format
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@ -506,7 +506,7 @@ class functional(simulation):
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# self.stim.gen_meas_value(meas_name=measure_name,
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# dout=signal_name,
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# t_initial=t_initial,
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# t_final=t_final)
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# t_final=t_final
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self.sf.write(".include {0}\n".format(temp_meas))
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self.stim.write_control(self.cycle_times[-1] + self.period)
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