mirror of https://github.com/VLSIDA/OpenRAM.git
Only add bitcells to dummy and replica rows and columns (the perimeter)
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parent
709535f90f
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051c8d8697
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@ -9,6 +9,7 @@ import debug
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import design
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from tech import cell_properties
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class bitcell_base_array(design.design):
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"""
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Abstract base class for bitcell-arrays -- bitcell, dummy
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@ -101,30 +102,11 @@ class bitcell_base_array(design.design):
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width=self.width,
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height=wl_pin.height())
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# For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space
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# Default uses prefered directions for each layer; this cell property is only currently used by sky130 tech (03/20)
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try:
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bitcell_power_pin_directions = cell_properties.bitcell_power_pin_directions
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except AttributeError:
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bitcell_power_pin_directions = None
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# For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps.
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try:
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end_caps_enabled = cell_properties.bitcell.end_caps
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except AttributeError:
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end_caps_enabled = False
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# Add vdd/gnd via stacks
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if not end_caps_enabled:
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for row in range(self.row_size):
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# Copy a vdd/gnd layout pin from every column in the first row
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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inst = self.cell_inst[0, col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin_name,
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loc=pin.center(),
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directions=bitcell_power_pin_directions,
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start_layer=pin.layer)
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self.copy_layout_pin(inst, pin_name)
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def _adjust_x_offset(self, xoffset, col, col_offset):
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tempx = xoffset
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@ -144,7 +126,6 @@ class bitcell_base_array(design.design):
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dir_x = True
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return (tempy, dir_x)
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def place_array(self, name_template, row_offset=0):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size * self.cell.height
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@ -156,7 +137,6 @@ class bitcell_base_array(design.design):
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(self.row_size):
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name = name_template.format(row, col)
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tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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if dir_x and dir_y:
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