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https://github.com/VLSIDA/OpenRAM.git
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Functional tests working with new RBL.
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@@ -53,8 +53,6 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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d = delay(s.s, tempspice, corner)
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feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
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f.num_cycles = 10
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(fail, error) = f.run()
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@@ -53,8 +53,6 @@ class psram_1bank_4mux_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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d = delay(s.s, tempspice, corner)
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feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
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f.num_cycles = 10
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(fail, error) = f.run()
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@@ -53,8 +53,6 @@ class psram_1bank_8mux_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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d = delay(s.s, tempspice, corner)
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feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
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f.num_cycles = 10
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(fail, error) = f.run()
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@@ -53,8 +53,6 @@ class psram_1bank_nomux_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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d = delay(s.s, tempspice, corner)
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feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
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f.num_cycles = 10
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(fail, error) = f.run()
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@@ -45,11 +45,9 @@ class sram_1bank_2mux_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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d = delay(s.s, tempspice, corner)
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feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
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f.num_cycles = 10
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(fail, error) = f.run(feasible_period)
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(fail, error) = f.run()
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self.assertTrue(fail,error)
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globals.end_openram()
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@@ -45,8 +45,6 @@ class sram_1bank_4mux_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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d = delay(s.s, tempspice, corner)
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feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
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f.num_cycles = 10
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(fail, error) = f.run()
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@@ -48,8 +48,6 @@ class sram_1bank_8mux_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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d = delay(s.s, tempspice, corner)
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feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
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f.num_cycles = 10
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(fail, error) = f.run()
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@@ -61,7 +61,7 @@ class openram_test(unittest.TestCase):
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self.fail("LVS mismatch: {}".format(a.name))
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# For debug...
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#import pdb; pdb.set_trace()
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import pdb; pdb.set_trace()
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if OPTS.purge_temp:
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self.cleanup()
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