Functional tests working with new RBL.

2026-09-01 02:28:31 +02:00 · 2019-07-12 08:42:36 -07:00
parent 0b13225913
commit 043018e8ba
18 changed files with 152 additions and 113 deletions
@@ -902,7 +902,13 @@ class pbitcell(design.design):
    
    def get_br_name(self, port=0):
        """Get bl name by port"""
-        return "br{}".format(port) 
+        return "br{}".format(port)
+
+    def get_wl_name(self, port=0):
+        """Get wl name by port"""
+        debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
+        return "wl{}".format(port)
+    

    def analytical_delay(self, corner, slew, load=0, swing = 0.5):
        parasitic_delay = 1