Functional tests working with new RBL.

compiler/bitcells/bitcell.py

@@ -71,7 +71,12 @@ class bitcell(design.design):
         """Get bl name"""
         debug.check(port==0,"One port for bitcell only.")
         return "br"  
-        
+
+    def get_wl_name(self, port=0):
+        """Get wl name"""
+        debug.check(port==0,"One port for bitcell only.")
+        return "wl"  
+    
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
         from tech import spice

compiler/bitcells/bitcell_1rw_1r.py

@@ -104,6 +104,11 @@ class bitcell_1rw_1r(design.design):
         """Get bl name by port"""
         debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
         return "br{}".format(port)
+
+    def get_wl_name(self, port=0):
+        """Get wl name by port"""
+        debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
+        return "wl{}".format(port)
     
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""

compiler/bitcells/bitcell_1w_1r.py

@@ -103,6 +103,11 @@ class bitcell_1w_1r(design.design):
         """Get bl name by port"""
         return "br{}".format(port)
     
+    def get_wl_name(self, port=0):
+        """Get wl name by port"""
+        debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
+        return "wl{}".format(port)
+    
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
         from tech import spice

compiler/bitcells/pbitcell.py

@@ -902,7 +902,13 @@ class pbitcell(design.design):
     
     def get_br_name(self, port=0):
         """Get bl name by port"""
-        return "br{}".format(port) 
+        return "br{}".format(port)
+
+    def get_wl_name(self, port=0):
+        """Get wl name by port"""
+        debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
+        return "wl{}".format(port)
+    
 
     def analytical_delay(self, corner, slew, load=0, swing = 0.5):
         parasitic_delay = 1