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Use readspice to define ports from sp netlist in Magic extract.

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mrg
2020-11-10 17:06:24 -08:00
parent 31ae56ff39
commit 03dad01e4c
5 changed files with 93 additions and 69 deletions
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compiler/tests/testutils.py
+1 -1
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@@ -48,7 +48,7 @@ class openram_test(unittest.TestCase):
# Run both DRC and LVS even if DRC might fail
# Magic can still extract despite DRC failing, so it might be ok in some techs
# if we ignore things like minimum metal area of pins
drc_result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification)
drc_result=verify.run_drc(a.name, tempgds, tempspice, extract=True, final_verification=final_verification)
# We can still run LVS even if DRC fails in Magic OR Calibre
lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification)