mirror of https://github.com/VLSIDA/OpenRAM.git
Fix indentation
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@ -26,7 +26,7 @@ class sram_multibank:
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'bank_sel': ceil(log(sram.num_banks, 2)),
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'num_wmask': sram.num_wmasks,
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'write_size': sram.write_size
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}
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}
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def verilog_write(self, name):
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template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "sram/sram_multibank_template.v")
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