mirror of https://github.com/VLSIDA/OpenRAM.git
Fix hard coded layer in wmask
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@ -126,7 +126,7 @@ class write_mask_and_array(design.design):
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for supply in ["gnd", "vdd"]:
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supply_pin_left = self.and2_insts[0].get_pin(supply)
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supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply)
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self.add_path("m1", [supply_pin_left.lc(), supply_pin_right.rc()])
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self.add_path(supply_pin_left.layer, [supply_pin_left.lc(), supply_pin_right.rc()])
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def get_cin(self):
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"""Get the relative capacitance of all the input connections in the bank"""
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