mirror of https://github.com/VLSIDA/OpenRAM.git
Editting comment on rule 5.5.b in scmos tech file. Adding complimentary rule to freepdk45 tech file.
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@ -106,6 +106,8 @@ drc["poly_to_active"] = 0.05
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drc["poly_to_field_poly"] = 0.075
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# Not a rule
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drc["minarea_poly"] = 0.0
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# Not a rule
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drc["poly_to_contactpoly"] = 0.075
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# ACTIVE.2 Minimum spacing of active
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drc["active_to_body_active"] = 0.08
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@ -83,7 +83,7 @@ drc["minwidth_poly"] = 0.6
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drc["poly_to_poly"] = 0.9
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# 3.3 Minimum gate extension of active
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drc["poly_extend_active"] = 0.6
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# ??
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# 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
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drc["poly_to_polycontact"] = 1.2
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# ??
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drc["active_enclosure_gate"] = 0.0
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