Fixed spacing in golden lib files. Added column mux into analytical model.

compiler/characterizer/delay.py

@@ -820,7 +820,7 @@ class delay(simulation):
         for slew in slews:
             for load in loads:
                 self.set_load_slew(load,slew)
-                bank_delay = sram.analytical_delay(self.slew,self.load)
+                bank_delay = sram.analytical_delay(self.vdd_voltage, self.slew,self.load)
                 # Convert from ps to ns
                 delay_lh.append(bank_delay.delay/1e3)
                 delay_hl.append(bank_delay.delay/1e3)

compiler/characterizer/lib.py

@@ -121,7 +121,7 @@ class lib:
         
     def write_footer(self):
         """ Write the footer """
-        self.lib.write("}\n") #Closing brace for the cell
+        self.lib.write("    }\n") #Closing brace for the cell
         self.lib.write("}\n") #Closing brace for the library
 
     def write_header(self):

compiler/example_config_scn4m_subm.py

@@ -10,9 +10,9 @@ output_path = "temp"
 output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
 
 #Setting for multiport
-# netlist_only = True
-# bitcell = "pbitcell"
-# replica_bitcell="replica_pbitcell"
-# num_rw_ports = 1
-# num_r_ports = 1
-# num_w_ports = 1
+netlist_only = True
+bitcell = "pbitcell"
+replica_bitcell="replica_pbitcell"
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 1

compiler/modules/bank.py

@@ -925,7 +925,7 @@ class bank(design.design):
                                 rotate=90)
 
         
-    def analytical_delay(self, slew, load):
+    def analytical_delay(self, vdd, slew, load):
         """ return  analytical delay of the bank"""
         decoder_delay = self.row_decoder.analytical_delay(slew, self.wordline_driver.input_load())
 
@@ -933,10 +933,17 @@ class bank(design.design):
 
         bitcell_array_delay = self.bitcell_array.analytical_delay(word_driver_delay.slew)
 
-        bl_t_data_out_delay = self.sense_amp_array.analytical_delay(bitcell_array_delay.slew,
+        if self.words_per_row > 1:
+            port = 0 #Analytical delay only supports single port
+            column_mux_delay = self.column_mux_array[port].analytical_delay(vdd, bitcell_array_delay.slew,
+                                                                     self.sense_amp_array.input_load())
+        else:
+            column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew)
+            
+        bl_t_data_out_delay = self.sense_amp_array.analytical_delay(column_mux_delay.slew,
                                                                     self.bitcell_array.output_load())
         # output load of bitcell_array is set to be only small part of bl for sense amp.
 
-        result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay 
+        result = decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay 
         return result
         

compiler/modules/sense_amp.py

@@ -23,6 +23,11 @@ class sense_amp(design.design):
         self.height = sense_amp.height
         self.pin_map = sense_amp.pin_map
 
+    def input_load(self):
+        #Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
+        bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
+        return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff   
+        
     def analytical_delay(self, slew, load=0.0):
         from tech import spice
         r = spice["min_tx_r"]/(10)

compiler/modules/sense_amp_array.py

@@ -134,6 +134,9 @@ class sense_amp_array(design.design):
                       width=self.width,
                       height=drc("minwidth_metal1"))
 
+    def input_load(self):
+        return self.amp.input_load()
+    
     def analytical_delay(self, slew, load=0.0):
         return self.amp.analytical_delay(slew=slew, load=load)
         

compiler/modules/single_level_column_mux_array.py

@@ -217,5 +217,13 @@ class single_level_column_mux_array(design.design):
                              offset= br_out_offset,
                              rotate=90)
 
+    def analytical_delay(self, vdd, slew, load=0.0):
+        from tech import spice
+        r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"])
+        #Drains of mux transistors make up capacitance. 
+        c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff
+        volt_swing = spice["v_threshold_typical"]/vdd
         
+        result = self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew, swing = volt_swing)
+        return self.return_delay(result.delay, result.slew)            
             

compiler/sram_base.py

@@ -451,8 +451,8 @@ class sram_base(design):
         sp.close()
 
         
-    def analytical_delay(self,slew,load):
+    def analytical_delay(self, vdd, slew,load):
         """ LH and HL are the same in analytical model. """
-        return self.bank.analytical_delay(slew,load)
+        return self.bank.analytical_delay(vdd,slew,load)
 
         

compiler/tests/26_pex_test.py

@@ -11,7 +11,7 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("SKIPPING 22_sram_pex_test")
+@unittest.skip("SKIPPING 26_pex_test")
 class sram_func_test(openram_test):
 
     def runTest(self):

compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_freepdk45){
             }
          }
     }
+
     }
 }

compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_freepdk45){
             }
          }
     }
+
     }
 }

compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_freepdk45){
             }
          }
     }
+
     }
 }

compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn3me_subm){
             }
          }
     }
+
     }
 }

compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn3me_subm){
             }
          }
     }
+
     }
 }

compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn3me_subm){
             }
          }
     }
+
     }
 }

compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn4m_subm){
             }
          }
     }
+
     }
 }

compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn4m_subm){
             }
          }
     }
+
     }
 }

compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib

@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn4m_subm){
             }
          }
     }
+
     }
 }

technology/freepdk45/tech/tech.py

@@ -295,6 +295,7 @@ spice["channel"] = drc["minlength_channel"]
 spice["clk"] = "clk"
 
 # analytical delay parameters
+spice["v_threshold_typical"] = 0.4    # Typical Threshold voltage in Volts
 spice["wire_unit_r"] = 0.075     # Unit wire resistance in ohms/square
 spice["wire_unit_c"] = 0.64      # Unit wire capacitance ff/um^2
 spice["min_tx_r"] = 9250.0       # Minimum transistor on resistance in ohms

technology/scn3me_subm/tech/tech.py

@@ -240,6 +240,7 @@ spice["clk"] = "clk"
 
 # analytical delay parameters
 # FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
+spice["v_threshold_typical"] = 1.3   # Typical Threshold voltage in Volts
 spice["wire_unit_r"] = 0.075    # Unit wire resistance in ohms/square
 spice["wire_unit_c"] = 0.64     # Unit wire capacitance ff/um^2
 spice["min_tx_r"] = 9250.0      # Minimum transistor on resistance in ohms

technology/scn4m_subm/tech/tech.py

@@ -261,6 +261,7 @@ spice["clk"] = "clk"
 
 # analytical delay parameters
 # FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
+spice["v_threshold_typical"] = 1.3   # Typical Threshold voltage in Volts
 spice["wire_unit_r"] = 0.075    # Unit wire resistance in ohms/square
 spice["wire_unit_c"] = 0.64     # Unit wire capacitance ff/um^2
 spice["min_tx_r"] = 9250.0      # Minimum transistor on resistance in ohms