Fixed spacing in golden lib files. Added column mux into analytical model.

compiler/modules/bank.py

@@ -925,7 +925,7 @@ class bank(design.design):
                                 rotate=90)
 
         
-    def analytical_delay(self, slew, load):
+    def analytical_delay(self, vdd, slew, load):
         """ return  analytical delay of the bank"""
         decoder_delay = self.row_decoder.analytical_delay(slew, self.wordline_driver.input_load())
 
@@ -933,10 +933,17 @@ class bank(design.design):
 
         bitcell_array_delay = self.bitcell_array.analytical_delay(word_driver_delay.slew)
 
-        bl_t_data_out_delay = self.sense_amp_array.analytical_delay(bitcell_array_delay.slew,
+        if self.words_per_row > 1:
+            port = 0 #Analytical delay only supports single port
+            column_mux_delay = self.column_mux_array[port].analytical_delay(vdd, bitcell_array_delay.slew,
+                                                                     self.sense_amp_array.input_load())
+        else:
+            column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew)
+            
+        bl_t_data_out_delay = self.sense_amp_array.analytical_delay(column_mux_delay.slew,
                                                                     self.bitcell_array.output_load())
         # output load of bitcell_array is set to be only small part of bl for sense amp.
 
-        result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay 
+        result = decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay 
         return result
         

compiler/modules/sense_amp.py

@@ -23,6 +23,11 @@ class sense_amp(design.design):
         self.height = sense_amp.height
         self.pin_map = sense_amp.pin_map
 
+    def input_load(self):
+        #Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
+        bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
+        return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff   
+        
     def analytical_delay(self, slew, load=0.0):
         from tech import spice
         r = spice["min_tx_r"]/(10)

compiler/modules/sense_amp_array.py

@@ -134,6 +134,9 @@ class sense_amp_array(design.design):
                       width=self.width,
                       height=drc("minwidth_metal1"))
 
+    def input_load(self):
+        return self.amp.input_load()
+    
     def analytical_delay(self, slew, load=0.0):
         return self.amp.analytical_delay(slew=slew, load=load)
         

compiler/modules/single_level_column_mux_array.py

@@ -217,5 +217,13 @@ class single_level_column_mux_array(design.design):
                              offset= br_out_offset,
                              rotate=90)
 
-                
+    def analytical_delay(self, vdd, slew, load=0.0):
+        from tech import spice
+        r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"])
+        #Drains of mux transistors make up capacitance. 
+        c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff
+        volt_swing = spice["v_threshold_typical"]/vdd
+        
+        result = self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew, swing = volt_swing)
+        return self.return_delay(result.delay, result.slew)