mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 format replica_bitcell_array
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mrg
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@ -32,8 +32,10 @@ class replica_bitcell_array(design.design):
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self.right_rbl = right_rbl
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self.bitcell_ports = bitcell_ports
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debug.check(left_rbl+right_rbl==len(self.all_ports),"Invalid number of RBLs for port configuration.")
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debug.check(left_rbl+right_rbl==len(self.bitcell_ports),"Bitcell ports must match total RBLs.")
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debug.check(left_rbl + right_rbl == len(self.all_ports),
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"Invalid number of RBLs for port configuration.")
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debug.check(left_rbl + right_rbl == len(self.bitcell_ports),
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"Bitcell ports must match total RBLs.")
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# Two dummy rows/cols plus replica for each port
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self.extra_rows = 2 + left_rbl + right_rbl
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@ -47,7 +49,6 @@ class replica_bitcell_array(design.design):
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# the replica bitcell in the control logic
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# self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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@ -118,7 +119,6 @@ class replica_bitcell_array(design.design):
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mirror=0)
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self.add_mod(self.dummy_row)
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# If there are bitcell end caps, replace the dummy cells on the edge of the bitcell array with end caps.
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try:
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end_caps_enabled = cell_properties.bitcell.end_caps
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@ -131,7 +131,7 @@ class replica_bitcell_array(design.design):
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self.edge_row = factory.create(module_type=edge_row_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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# dummy column + left replica column(s)
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column_offset=1 + self.left_rbl,
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mirror=0)
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self.add_mod(self.edge_row)
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@ -149,9 +149,9 @@ class replica_bitcell_array(design.design):
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self.edge_col_right = factory.create(module_type=edge_col_module_type,
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cols=1,
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# dummy column
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# + left replica column
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# + left replica column(s)
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# + bitcell columns
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# + right replica column
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# + right replica column(s)
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column_offset = 1 + self.left_rbl + self.column_size + self.right_rbl,
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl + 1) %2)
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@ -195,7 +195,6 @@ class replica_bitcell_array(design.design):
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# Left/right dummy columns are connected identically to the replica column
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self.dummy_col_wl_names = self.replica_col_wl_names
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# Per port bitline names
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self.replica_bl_names = {}
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self.replica_wl_names = {}
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@ -211,10 +210,8 @@ class replica_bitcell_array(design.design):
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self.replica_bl_names[port] = bl_names
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wl_names = ["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()]
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#wl_names[port] = "rbl_wl{}".format(port)
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self.replica_wl_names[port] = wl_names
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# External pins
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self.add_pin_list(self.bitcell_array_bl_names, "INOUT")
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# Need to sort by port order since dictionary values may not be in order
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@ -231,7 +228,6 @@ class replica_bitcell_array(design.design):
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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""" Create the module instances used in this design """
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@ -252,7 +248,6 @@ class replica_bitcell_array(design.design):
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mod=self.replica_columns[port])
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self.connect_inst(self.replica_bl_names[port] + self.replica_col_wl_names + supplies)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_inst = {}
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for port in range(self.left_rbl + self.right_rbl):
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@ -260,7 +255,6 @@ class replica_bitcell_array(design.design):
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + self.replica_wl_names[port] + supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_bot_inst=self.add_inst(name="dummy_row_bot",
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mod=self.edge_row)
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@ -269,7 +263,6 @@ class replica_bitcell_array(design.design):
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mod=self.edge_row)
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self.connect_inst(self.dummy_row_bl_names + [x + "_top" for x in self.dummy_cell_wl_names] + supplies)
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# Left/right Dummy columns
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self.dummy_col_left_inst=self.add_inst(name="dummy_col_left",
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mod=self.edge_col_left)
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@ -295,10 +288,12 @@ class replica_bitcell_array(design.design):
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for bit in range(self.right_rbl):
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self.replica_col_inst[self.left_rbl + bit].place(offset=offset.scale(bit, -self.left_rbl - 1) + self.bitcell_array_inst.lr())
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# FIXME: These depend on the array size itself
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# Far top dummy row (first row above array is NOT flipped)
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flip_dummy = self.right_rbl % 2
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self.dummy_row_top_inst.place(offset=offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul(),
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mirror="MX" if flip_dummy else "R0")
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# FIXME: These depend on the array size itself
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# Far bottom dummy row (first row below array IS flipped)
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flip_dummy = (self.left_rbl + 1) % 2
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self.dummy_row_bot_inst.place(offset=offset.scale(0, -self.left_rbl - 1 + flip_dummy),
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@ -316,7 +311,6 @@ class replica_bitcell_array(design.design):
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self.dummy_row_replica_inst[self.left_rbl + bit].place(offset=offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(),
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mirror="MX" if bit % 2 else "R0")
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self.translate_all(offset.scale(-1 - self.left_rbl, -1 - self.left_rbl))
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self.add_layout_pins()
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@ -325,7 +319,6 @@ class replica_bitcell_array(design.design):
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self.DRC_LVS()
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def add_layout_pins(self):
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""" Add the layout pins """
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@ -351,7 +344,6 @@ class replica_bitcell_array(design.design):
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width=pin.width(),
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height=self.height)
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# Replica wordlines
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for port in range(self.left_rbl + self.right_rbl):
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inst = self.replica_col_inst[port]
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@ -416,8 +408,6 @@ class replica_bitcell_array(design.design):
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc, parameter
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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