Modified pinvbuf to have a stage effort of 4 for driving the

clock bar to wordline enable.
Fixed comments in stimulus file to have right cycle numbers.
Removed clock gating on we signal since clock gating is already
done on the WL signals. It is redundant.

compiler/characterizer/delay.py

@@ -661,11 +661,11 @@ class delay():
 
         # One period
         msg = "Idle cycle (Read addr 00..00)"
+        self.cycle_times.append(t_current)
+        self.idle_cycle=len(self.cycle_times)-1        
         self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
                                                                   t_current,
                                                                   msg))
-        self.cycle_times.append(t_current)
-        self.idle_cycle=len(self.cycle_times)-1        
         t_current += self.period
 
         # One period